|
Your ML506 Evaluation Platform is a general purpose board that ships with a number of demonstration designs pre-installed on the Compact Flash card, Platform Flash, and Linear Flash memories. The ML506 Getting Started Tutorial describes how to quickly get started using your ML506. This tutorial also contains a number of hands-on user lab exercises to help you explore the features of your ML506.
 ML506 Getting Started Tutorial
ML506 QuickStart
 ML506 Lab Resources |
 |
|
The Xilinx Base System Builder (BSB) wizard helps users quickly build a working embedded processing system design through an easy to use GUI interface. The XPS project created by BSB can be run as generated or further enhanced with peripherals added from the EDK IP catalog.
Please see Answer Record # 34466 for the ISE 12.1 Design Suite Known Issues.
ML506 Reference Design User Guide
ML506 Overview and Setup
 Master UCF Pin Constraints
EDK 12.1 / ISE 12.1
|
|
|
Tutorial on using the Xilinx System Generator for DSP with the ML506 board to create and test a Hardware Co-simulation
Sysgen 12.1
|
|
|
The ML506 Evaluation Platform is built around the Virtex-5 XC5VSX50T FPGA with high performance RocketIO™ GTP transceivers. This design contains a tutorial demonstrating how to generate an IBERT design that exercises the GTP transceivers using the ChipScope™ Pro Serial IO Toolkit.
|
|
|
Using the Xilinx Core Generator™ Memory Interface Generator to build a DDR2 design. Includes ChipScope Pro addition and testing.
|
|
|
A Xilinx CORE Generator™ design is shown that leverages both the hardened PCIe Endpoint Block and a high-performance RocketIO GTP transceiver to create a single-lane PCI Express x1 Endpoint.
|
|
|
This Quickstart utilizes the ChipScope Pro System Monitor Console to display device voltages, temperatures, and external signal levels. The System Monitor feature is built into all Virtex-5 devices.
ML506 System Monitor Quickstart |
|
|
The ML506 can be used to demonstrate a variety of Virtex-5 configuration methods. Initial board bring-up and testing can be accomplished with the Xilinx tools, a JTAG cable, along with the bitstreams and ELF files from the ML506 standalone applications page. Subsequently, ACE files containing both hardware and software initialization components can be generated and loaded from a CompactFlash card by the onboard System ACE™ CF controller. A new Virtex-5 configuration method loads bitstreams directly from a linear flash memory device. Demonstrating the various Virtex-5 configuration methods is user-selectable through a DIP switch.
|
Virtex-5 Configuration User Guide
|
