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The Integrated Bit Error Ratio Tester (IBERT) designs provide users access to the Virtex-5 RocketIO™ GTX transceivers. The IBERT core contains pattern generators and checkers that exercise the high-speed serial GTX transceivers. In addition, the attributes of each RocketIO transceiver can be accessed through the IBERT console.
IBERT design creation and verification using loopback and test equipment available from third-party vendors. This IBERT design includes GTX transceivers associated with the SGMII, SMA, SFP, PCIe, and onboard loopback interfaces.
 ML507 4GTXs IBERT QuickStart
ML507 4GTXs IBERT Design Creation
 ml507_ibert_4gtxs_design.zip
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