Your ML507 Evaluation Platform is a general purpose board that ships with a number of demonstration designs pre-installed on the Compact Flash card, Platform Flash, and Linear Flash memories. The ML507 Getting Started Tutorial describes how to quickly get started using your ML507. This tutorial also contains a number of hands-on user lab exercises to help you explore the features of your ML507.
The Xilinx Base System Builder (BSB) wizard helps users quickly build a working embedded processing system design through an easy to use GUI interface. The XPS project created by BSB can be run as generated or further enhanced with peripherals added from the EDK IP catalog.
Please see Answer Record # 34466 for the ISE 12.1 Design Suite Known Issues.
The following ZIP files include Linux reference designs targeting both the Virtex®-5 PPC 440 and MicroBlaze™. Each as a hardware platform and a software project that include a HelloWorld software project that exercises various features of the development board, and a Linux software project that demonstrates a BlueCat Linux image with simple network functions over the Ethernet port, an Apache Web server that can serve up a web page, and other standard Linux file functions.
The ML507 BSB PPC440 design with Workbench 2.5 VxWorks design files.
The ML507 Evaluation Platform is built around the Virtex-5 XC5VFX70T FPGA with high performance RocketIO™ GTX transceivers. This design contains a tutorial demonstrating how to generate an IBERT design that exercises the GTX transceivers using the ChipScope™ Pro Serial IO Toolkit.
Using the CORE Generator™ Memory Interface Generator to build a DDR2 design. Includes ChipScope Pro addition and testing.
A Xilinx CORE Generator design is shown that leverages both the hardened PCIe® Endpoint Block and a high-performance RocketIO GTX transceiver to create a single-lane PCI Express x1 Endpoint.
This Quickstart utilizes the ChipScope Pro System Monitor Console to display device voltages, temperatures, and external signal levels. The System Monitor feature is built into all Virtex-5 devices.
The ML507 can be used to demonstrate a variety of Virtex-5 configuration methods. Initial board bring-up and testing can be accomplished with the Xilinx tools, a JTAG cable, along with the bitstreams and ELF files from the ML507 standalone applications page. Subsequently, ACE files containing both hardware and software initialization components can be generated and loaded from a CompactFlash card by the onboard System ACE™ CF controller. A new Virtex-5 configuration method loads bitstreams directly from a linear flash memory device. Demonstrating the various Virtex-5 configuration methods is user-selectable through a DIP switch.