Xilinx ML510 Base System Builder Designs - 10.1 SP3
ML510 Stand-Alone Applications & Board Tests
Built upon the ML510 BSB and EDK's automatically generated library of device drivers and platform support, these Stand-Alone software applications can be used to gain familiarity with the EDK software development tools while exercising features on the ML510 board.
- ML510 MicroBlaze Stand-Alone Applications & Board Tests
- ML510 PPC440 Stand-Alone Applications & Board Tests
ML510 Embedded Reference Designs
Tutorials describing how to use Base System Builder (BSB) to create MicroBlaze and PowerPC embedded systems using EDK are presented on this web page. The basic BSB generated hardware design is then used to create a derivative design that adds standard IP. Using the standard IP design as a starting point, pcores are added to generate the Pcores example design. For each design, a zip file containing the results of running through the tutorials is provided.A tutorial and results zip file, showing how to create a dual processor system with two independent BSB generated processing systems is also available in the ML510 Dual Design (BSB1 + BSB2) section. The dual processor design is created by merging two independent single-processor BSB designs, BSB1 and BSB2, into a single design containing two independent processing systems.
ML510 BSB1 Designs
| ML510 BSB1 Design | |
|---|---|
| BSB1 MicroBlaze IP | BSB1 PPC440 IP |
| microblaze - 125 MHz | ppc440_virtex5 - 300 MHz |
| mpmc - 125 MHz | ppc440mc_ddr2 - 200 MHz |
| plb_v46 - 125 MHz | plb_v46 - 100 MHz |
| lmb_bram_if_cntlr | xps_bram_if_cntlr |
| bram_block | bram_block |
| clock_generator | clock_generator |
| proc_sys_reset | proc_sys_reset |
| util_bus_split | util_bus_split |
| util_reduced_logic | util_reduced_logic |
| xps_gpio | xps_gpio |
| xps_iic | xps_iic |
| xps_intc | xps_intc |
| xps_ll_temac | xps_ll_temac |
| xps_mch_emc | xps_mch_emc |
| xps_spi | xps_spi |
| xps_sysace | xps_sysace |
| xps_uart16550 | xps_uart16550 |
| lmb_v10 | xps_ll_fifo |
| xps_timer | jtagppc_cntlr |
| mdm | |
A tutorial with design files shows how to utilize the XPS BSB wizard to generate a single-processor embedded processing system. The BSB1 hardware design uses one set of the two available integrated processors, DIMM memories, Ethernet connections, and UARTs on the ML510. This design is the foundation upon which additional designs in the BSB1 section are built.
| ML510 BSB1 Design Creation (PDF) ml510_bsb1_design.zip (ZIP) |
 |
| ML510 BSB1 PPC440 Design Creation (PDF) ml510_bsb1_design_ppc440.zip (ZIP) |
 |
ML510 BSB1 Standard IP Design
| Standard IP Added or Modified |
| xps_tft |
| util_vector_logic |
| clock_generator |
| xps_ll_temac |
| proc_sys_reset |
This design starts with the results of the initial BSB GUI generated BSB1 design and adds or modifies this design through the application of Answer Records and/or standard supported IP from the EDK IP catalog using XPS. The tutorial also demonstrates how to change the default BSB Gigabit Ethernet PHY interface from MII to RGMII.
| ML510 BSB1 Std IP Addition (PDF) ml510_bsb1_std_ip.zip (ZIP) |
|
| ML510 BSB1 PPC440 Std IP Addition (PDF) ml510_bsb1_std_ip_ppc440.zip (ZIP) |
|
ML510 BSB1 Pcores Design
| Standard IP and Pcores Added or Modified |
| plbv46_pci (Pcore) |
| pci_arbiter |
| clock_generator |
| xps_intc |
This derivative design builds on the standard IP design and adds additional IP as custom pcores through XPS. An updated PCI core is introduced along with supporting hardware.
| ML510 BSB1 Pcores Addition (PDF) ml510_bsb1_pcores.zip (ZIP) |
|
| ML510 BSB1 PPC440 Pcores Addition (PDF) ml510_bsb1_pcores_ppc440.zip (ZIP) |
|
ML510 BSB2 Designs
The BSB2 hardware design uses the second set of the two available integrated processors, DIMM memories, Ethernet connections, and UARTs on the ML510. This design is the foundation upon which additional designs in the BSB2 section are built.
The BSB2 designs access the second set of ML510 processor resources through the BSB GUI using the XBD zip file provided below.
ML510 DIMM1 XBD Files
DIMM1 XBD files required for Base System Builder to target the ML510 board. Unzip to your $XILINX_EDK directory.
Xilinx_ML510_DIMM1_v2_2_0.zip (ZIP)ML510 BSB2 Design
| BSB2 MicroBlaze IP | BSB2 PPC440 IP |
| microblaze - 125 MHz | ppc440_virtex5 - 300 MHz |
| mpmc - 125 MHz | ppc440mc_ddr2 - 200 MHz |
| plb_v46 - 125 MHz | plb_v46 - 100 MHz |
| lmb_bram_if_cntlr | xps_bram_if_cntlr |
| bram_block | bram_block |
| clock_generator | clock_generator |
| proc_sys_reset | proc_sys_reset |
| util_reduced_logic | util_reduced_logic |
| xps_intc | xps_intc |
| xps_ll_temac | xps_ll_temac |
| xps_sysace | xps_sysace |
| xps_uart16550 | xps_uart16550 |
| lmb_v10 | xps_ll_fifo |
| xps_timer | jtagppc_cntlr |
| mdm |
A tutorial with design files shows how to utilize the XPS BSB wizard along with the provided XBD files to generate a single-processor embedded processing system. The BSB2 hardware design uses the second set of the two available integrated processors, DIMM memories and UARTs.
| ML510 BSB2 Design Creation (PDF) ml510_bsb2_design.zip (ZIP) |
|
| ML510 BSB2 PPC440 Design Creation (PDF) ml510_bsb2_design_ppc440.zip (ZIP) |
|
ML510 BSB2 Standard IP Design
This design starts with the results of the initial BSB GUI generated BSB2 design and adds or modifies this design through the application of Answer Records and/or standard supported IP from the EDK IP catalog using XPS. The tutorial also demonstrates how to change the default BSB Gigabit Ethernet PHY interface from MII to SGMII.
| ML510 BSB2 Std IP Addition (PDF) ml510_bsb2_std_ip.zip (ZIP) |
|
| ML510 BSB2 PPC440 Std IP Addition (PDF) ml510_bsb2_std_ip_ppc440.zip (ZIP) |
|
ML510 Dual Design (BSB1 + BSB2)
| ML510 Dual Processor Design | |
|---|---|
| BSB1 MicroBlaze IP | BSB1 PPC440 IP |
| microblaze - 125 MHz | ppc440_virtex5 - 300 MHz |
| mpmc - 125 MHz | ppc440mc_ddr2 - 200 MHz |
| plb_v46 - 125 MHz | plb_v46 - 100 MHz |
| lmb_bram_if_cntlr | xps_bram_if_cntlr |
| bram_block | bram_block |
| clock_generator | clock_generator |
| proc_sys_reset | proc_sys_reset |
| util_bus_split | util_bus_split |
| util_reduced_logic | util_reduced_logic |
| xps_gpio | xps_gpio |
| xps_iic | xps_iic |
| xps_intc | xps_intc |
| xps_ll_temac | xps_ll_temac |
| xps_mch_emc | xps_mch_emc |
| xps_spi | xps_spi |
| xps_sysace | xps_sysace |
| xps_uart16550 | xps_uart16550 |
| lmb_v10 | xps_ll_fifo |
| xps_timer | jtagppc_cntlr |
| mdm | xps_tft |
| xps_tft | plbv46_pci (Pcore) |
| plbv46_pci (Pcore) | pci_arbiter |
| pci_arbiter | util_vector_logic |
| util_vector_logic | |
| 2nd MicroBlaze IP | 2nd PPC440 IP |
| microblaze - 125 MHz | ppc440_virtex5 - 300 MHz |
| mpmc - 125 MHz | ppc440mc_ddr2 - 200 MHz |
| plb_v46 - 125 MHz | plb_v46 - 100 MHz |
| lmb_bram_if_cntlr | xps_bram_if_cntlr |
| bram_block | bram_block |
| proc_sys_reset | proc_sys_reset |
| xps_intc | xps_intc |
| xps_ll_temac | xps_ll_temac |
| xps_uart16550 | xps_uart16550 |
| lmb_v10 | xps_ll_fifo |
| xps_timer | |
The ML510 dual-processor designs are generated by merging the BSB1 Pcores and BSB2 Standard IP designs. Both sets of independent ML510 processors, DIMM memories, Ethernet connections, and UARTs, are active in this dual independent processing system design. RGMII and SGMII interfaces are used for the Gigabit Ethernet PHY connections.
| ML510 Dual MicroBlaze Design (PDF) ml510_dual_design.zip (ZIP) |
|
| ML510 Dual PPC440 Design (PDF) ml510_dual_design_ppc440.zip (ZIP) |
|