******************************************************************************* ** Copyright © 2008, Xilinx, Inc. ** This design is confidential and proprietary of Xilinx, Inc. All Rights Reserved. ******************************************************************************* ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ Version: 1.0 ** \ \ Filename: hello_pci_readme.txt ** / / ** /___/ /\ ** \ \ / \ ** \___\/\___\ ** **Device: **Purpose: **Reference: ** ******************************************************************************* ** ** Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are ** provided to you "as is." Xilinx and its licensors make and you ** receive no warranties or conditions, express, implied, ** statutory or otherwise, and Xilinx specifically disclaims any ** implied warranties of merchantability, noninfringement, or ** fitness for a particular purpose. Xilinx does not warrant that ** the functions contained in these designs will meet your ** requirements, or that the operation of these designs will be ** uninterrupted or error free, or that defects in the Designs ** will be corrected. Furthermore, Xilinx does not warrant or ** make any representations regarding use or the results of the ** use of the designs in terms of correctness, accuracy, ** reliability, or otherwise. ** ** LIMITATION OF LIABILITY. In no event will Xilinx or its ** licensors be liable for any loss of data, lost profits, cost ** or procurement of substitute goods or services, or for any ** special, incidental, consequential, or indirect damages ** arising from the use or operation of the designs or ** accompanying documentation, however caused and on any theory ** of liability. This limitation will apply even if Xilinx ** has been advised of the possibility of such damage. This ** limitation shall apply notwithstanding the failure of the ** essential purpose of any limited remedies herein. ** ******************************************************************************* Application: hello_pci ---------------------- Scans PCI bus. CONFIG Switch Settings: 00010101 1. Connect the Host PC to the ML510 (J9 header) using a PC-IV or Platform USB JTAG cable 2. Connect the Host PC serial port to the ML510 serial port using a null modem cable and launch a terminal program on the Host (eg. TeraTerm) with the settings: 9600 baud, 8-N-1, No flow control 3. Launch XPS and open the ML510 EDK project (ml510_bsb_system.xmp) 4. Launch a Shell window using XPS menu selection: Project > Launch EDK Shell 5. Download bitstream in shell window by typing: impact -batch etc/download.cmd 6. XPS menu selection: Debug > Launch XMD 7. At XMD% prompt type: dow microblaze_0/code/hello_pci.elf 8. At XMD% prompt type: con Serial Port Output: ------------------- PCI Test: Scan PCI Config Regs of ML510 Xilinx PCI Core (AD16): Offset=00:051010EE Offset=04:02000000 Offset=08:0600001A Offset=0C:00000000 Offset=10:00000008 Offset=14:00000000 Offset=18:00000000 Offset=1C:00000000 Offset=20:00000000 Offset=24:00000000 Offset=28:00000000 Offset=2C:051010EE Offset=30:00000000 Offset=34:00000000 Offset=38:00000000 Offset=3C:543201FF Enable Master Transactions on Xilinx PCI Core: Status/Command Reg of Xilinx PCI Core = 02000146 Set Max LAT Timer on Xilinx PCI Core: Status Reg (0xC) in Xilinx PCI Core = 0000FF00 Set Bus Num and Subordinate bus Num on Xilinx PCI Core: Bus Num/Sub Bus Num Reg (0x114) in Xilinx PCI Core = 01000000 Scan PCI Config Regs of South Bridge (AD18): Offset=00:153310B9 Offset=04:0210000F Offset=08:06010000 Offset=0C:00000000 Offset=10:00000000 Offset=14:00000000 Offset=18:00000000 Offset=1C:00000000 Offset=20:00000000 Offset=24:00000000 Offset=28:00000000 Offset=2C:153310B9 Offset=30:00000000 Offset=34:000000A0 Offset=38:00000000 Offset=3C:00000000 Scan PCI Config Regs of TI Bridge (AD25): Offset=00:AC23104C Offset=04:02100000 Offset=08:06040002 Offset=0C:00010000 Offset=10:00000000 Offset=14:00000000 Offset=18:00000000 Offset=1C:02000101 Offset=20:00000000 Offset=24:00000000 Offset=28:00000000 Offset=2C:00000000 Offset=30:00000000 Offset=34:000000DC Offset=38:00000000 Offset=3C:000000FF Scan PCI Config Regs of ML510 3.3v PCI Slot 3 (AD22): Offset=00:FFFFFFFF Offset=04:FFFFFFFF Offset=08:FFFFFFFF Offset=0C:FFFFFFFF Offset=10:FFFFFFFF Offset=14:FFFFFFFF Offset=18:FFFFFFFF Offset=1C:FFFFFFFF Offset=20:FFFFFFFF Offset=24:FFFFFFFF Offset=28:FFFFFFFF Offset=2C:FFFFFFFF Offset=30:FFFFFFFF Offset=34:FFFFFFFF Offset=38:FFFFFFFF Offset=3C:FFFFFFFF Scan PCI Config Regs of ML510 3.3v PCI Slot 5 (AD21): Offset=00:FFFFFFFF Offset=04:FFFFFFFF Offset=08:FFFFFFFF Offset=0C:FFFFFFFF Offset=10:FFFFFFFF Offset=14:FFFFFFFF Offset=18:FFFFFFFF Offset=1C:FFFFFFFF Offset=20:FFFFFFFF Offset=24:FFFFFFFF Offset=28:FFFFFFFF Offset=2C:FFFFFFFF Offset=30:FFFFFFFF Offset=34:FFFFFFFF Offset=38:FFFFFFFF Offset=3C:FFFFFFFF Setup TI Bridge Control/status (AD25): TI Bridge Reg offset 0x04 = 02100007 Setup TI Bridge Bus Number (AD25): TI Bridge Reg offset 0x18 = 00010100 Scan PCI Config Regs of ML510 5.0v PCI Slot 4 (AD19): Offset=00:FFFFFFFF Offset=04:FFFFFFFF Offset=08:FFFFFFFF Offset=0C:FFFFFFFF Offset=10:FFFFFFFF Offset=14:FFFFFFFF Offset=18:FFFFFFFF Offset=1C:FFFFFFFF Offset=20:FFFFFFFF Offset=24:FFFFFFFF Offset=28:FFFFFFFF Offset=2C:FFFFFFFF Offset=30:FFFFFFFF Offset=34:FFFFFFFF Offset=38:FFFFFFFF Offset=3C:FFFFFFFF Scan PCI Config Regs of ML510 5.0v PCI Slot 6 (AD18): Offset=00:FFFFFFFF Offset=04:FFFFFFFF Offset=08:FFFFFFFF Offset=0C:FFFFFFFF Offset=10:FFFFFFFF Offset=14:FFFFFFFF Offset=18:FFFFFFFF Offset=1C:FFFFFFFF Offset=20:FFFFFFFF Offset=24:FFFFFFFF Offset=28:FFFFFFFF Offset=2C:FFFFFFFF Offset=30:FFFFFFFF Offset=34:FFFFFFFF Offset=38:FFFFFFFF Offset=3C:FFFFFFFF