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The Integrated Bit Error Ratio Tester (IBERT) designs provide users access to the Virtex-5 RocketIO™ GTX transceivers. The IBERT core contains pattern generators and checkers that exercise the high-speed serial GTX transceivers. In addition, each RocketIO transceiver’s attributes can be accessed through the IBERT console.
IBERT design creation and verification using loopback and test equipment available from third-party vendors. This IBERT design includes GTX transceivers associated with the SGMII and SATA, and onboard loopback interfaces.
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