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| Built upon the ML510 BSB and EDK's automatically generated library of device drivers and platform support, these Stand-Alone software applications can be used to gain familiarity with the EDK software development tools while exercising features on the ML510 board.
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Tutorials describing how to use Base System Builder (BSB) to create MicroBlaze and PowerPC embedded systems using EDK are presented on this web page. The basic BSB generated hardware design is then used to create a derivative design that adds standard IP. Using the standard IP design as a starting point, pcores are added to generate the Pcores example design. For each design, a zip file containing the results of running through the tutorials is provided.
A tutorial and results zip file, showing how to create a dual processor system with two independent BSB generated processing systems is also available in the ML510 Dual Design (BSB1 + BSB2) section. The dual processor design is created by merging two independent single-processor BSB designs, BSB1 and BSB2, into a single design containing two independent processing systems. |
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BSB1 MicroBlaze IP
- microblaze - 125 MHz
- mpmc - 125 MHz
- plb_v46 - 125 MHz
- plbv46_pci
- pci_arbiter
- xps_central_dma
- lmb_bram_if_cntlr
- bram_block
- clock_generator
- proc_sys_reset
- util_bus_split
- util_reduced_logic
- xps_gpio
- xps_iic
- xps_intc
- xps_ll_temac
- xps_mch_emc
- xps_spi
- xps_sysace
- xps_uart16550
- lmb_v10
- xps_timer
- mdm
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A tutorial with design files shows how to utilize the XPS BSB wizard to generate a single-processor embedded processing system. The BSB1 hardware design uses one set of the two available integrated processors, DIMM memories, Ethernet connections, and UARTs on the ML510. This design is the foundation upon which additional designs in the BSB1 section are built.
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Standard IP Added or Modified
- clock_generator
- xps_ll_temac
- util_vector_logic
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This design starts with the results of the initial BSB GUI generated BSB1 design and adds or modifies this design through the application of Answer Records and/or standard supported IP from the EDK IP catalog using XPS. The tutorial also demonstrates how to change the default BSB Gigabit Ethernet PHY interface from MII to RGMII.
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This tutorial shows how to generate a VxWorks 6.3 Board Support Package (BSP) within EDK for the PPC440 BSB1 Std IP hardware build. The tutorial also provides instructions on how to create a VxWorks system image using Wind River’s Workbench environment.
The pre-built bitstream, ACE file, VxWorks BSP and Workbench project and executable VxWorks ELF file are provided below. The overlay zip file is provided as a convenience for users running through the tutorial to re-create the pre-built result files.
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The BSB2 hardware design uses the second set of the two available integrated processors, DIMM memories, Ethernet connections, and UARTs on the ML510. This design is the foundation upon which additional designs in the BSB2 section are built.
The BSB2 designs access the second set of ML510 processor resources through the BSB GUI using the XBD zip file provided below. |
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DIMM1 XBD files required for Base System Builder to target the ML510 board. Unzip to your $XILINX_EDK directory.
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BSB2 MicroBlaze IP
- microblaze - 125 MHz
- mpmc - 125 MHz
- plb_v46 - 125 MHz
- lmb_bram_if_cntlr
- bram_block
- clock_generator
- proc_sys_reset
- util_reduced_logic
- xps_intc
- xps_ll_temac
- xps_sysace
- xps_uart16550
- lmb_v10
- xps_timer
- mdm
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A tutorial with design files shows how to utilize the XPS BSB wizard along with the provided XBD files to generate a single-processor embedded processing system. The BSB2 hardware design uses the second set of the two available integrated processors, DIMM memories and UARTs.
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This design starts with the results of the initial BSB GUI generated BSB2 design and adds or modifies this design through the application of Answer Records and/or standard supported IP from the EDK IP catalog using XPS. The tutorial also demonstrates how to change the default BSB Gigabit Ethernet PHY interface from MII to SGMII.
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This tutorial shows how to generate a VxWorks 6.3 Board Support Package (BSP) within EDK for the PPC440 BSB2 Standard IP hardware build. The tutorial also provides instructions on how to create a VxWorks system image using Wind River’s Workbench 2.5 environment.
The pre-built bitstream, ACE file, VxWorks BSP and Workbench project and executable VxWorks ELF file are provided below. The overlay zip file is provided as a convenience for users running through the tutorial to re-create the pre-built result files.
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1st MicroBlaze IP
- microblaze - 125 MHz
- mpmc - 125 MHz
- plb_v46 - 125 MHz
- plbv46_pci
- pci_arbiter
- xps_tft
- xps_central_dma
- lmb_bram_if_cntlr
- bram_block
- clock_generator
- proc_sys_reset
- util_vector_logic
- util_reduced_logic
- xps_gpio
- xps_iic
- xps_intc
- xps_ll_temac
- xps_mch_emc
- xps_spi
- xps_sysace
- xps_uart16550
- lmb_v10
- xps_timer
- mdm
2nd MicroBlaze IP
- microblaze - 125 MHz
- mpmc - 125 MHz
- plb_v46 - 125 MHz
- lmb_bram_if_cntlr
- bram_block
- proc_sys_reset
- util_reduced_logic
- xps_intc
- xps_ll_temac
- xps_uart16550
- lmb_v10
- xps_timer
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The ML510 dual-processor designs are generated by merging the BSB1 Pcores and BSB2 Standard IP designs. Both sets of independent ML510 processors, DIMM memories, Ethernet connections, and UARTs, are active in this dual independent processing system design. RGMII and SGMII interfaces are used for the Gigabit Ethernet PHY connections.
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This tutorial shows how to generate a VxWorks 6.3 Board Support Package (BSP) within EDK for the dual independent processing system (BSB1 + BSB2) PPC440 hardware build. The tutorial also provides instructions on how to create VxWorks system images for each processing system using Wind River’s Workbench 2.5 environment.
The pre-built bitstream, ACE file, VxWorks BSP and Workbench project and executable VxWorks ELF file are provided below. The overlay zip file is provided as a convenience for users running through the tutorial to re-create the pre-built result files.
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