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Spartan-6 FPGA Connectivity Kit Reference Design and Documentation

Xilinx Boards and Kits
The Spartan®-6 FPGA Connectivity Kit enables faster design development and provides a jump-start through the connectivity targeted reference design included in it.

Note: For information on upgrading from the Spartan-6 FPGA ML605 Evaluation Kit or other domain-specific Spartan®-6 design platform, see the specific steps at the bottom of this page.
Reference Design & Documentation ISE® Design Suite 12.2 ISE Design Suite 12.1
Spartan-6 FPGA Connectivity Targeted Reference Design
This is a x1PCIe-DMA-DDR3-GbE that enables turnkey implementations with the main integrated components in a Spartan-6 FPGA—the endpoint block for PCI Express, the GTP transceivers, and the memory controller block working together in an application with additional IP cores such as a third-party (Northwest Logic) Packet DMA engine for the PCI Express interface, XPS-LL-TEMAC (using the LogiCORE IP Tri-mode Ethernet MAC) and Memory Interface Generator (MIG) tool. Spartan-6 LXT FPGA: CES Silicon
(Reference Design & Documentation)
(zip)
Spartan-6 LXT FPGA: CES Silicon
(Reference Design & Documentation)
(zip)
Spartan-6 LXT FPGA: Production Silicon
(Reference Design & Documentation)
(zip)
Spartan-6 LXT FPGA: Production Silicon
(Reference Design & Documentation)
(zip)
Spartan-6 FPGA Connectivity Kit Hardware Setup Guide
The Spartan-6 FPGA Connectivity Kit Hardware Setup Guide provides a step by step hardware setup and overview of the Kit. Hardware setup guide(pdf) Hardware setup guide(pdf)
Spartan-6 FPGA Connectivity Kit Getting Started Guide
The Spartan-6 FPGA Connectivity Kit Getting Started Guide provides hardware setup steps and step by step overview of the Connectivity Targeted Reference Design. It covers the steps for the Installation of the Software as well as where to find additional resources. ug665 (v1.3) (pdf) ug665 (v1.1) (pdf)
Spartan-6 FPGA Connectivity Kit Reference Design User Guide

The Spartan-6 FPGA Connectivity Targeted Reference Design is a fully operational bridge between the PCIe and GbE IP blocks that provides an efficient platform for evaluating the key integrated components in a Spartan-6 FPGA device.

  • GTP transceivers
  • Endpoint Block for PCIe
  • Memory Controller Block supporting DDR/DDR2/DDR3 and LPDDR
  • Bus Mastering PCIe Packet DMA engine from Northwest Logic (optimized for Spartan-6 FPGA)
  • Xilinx Platform Studio LocalLink Tri-Mode Ethernet MAC (XPS-LL-TEMAC).
ug392 (v1.4) (pdf) ug392 (v1.3) (pdf)
Additional Documentation
This includes SP605 FPGA Board User Guide, Schematics, PCB files as well as other base reference designs like IBERT and BIST designs. Spartan-6 FPGA Evaluation Kit Documentation
This includes Embedded Targeted Reference designs including Microblaze® Processor Sub-system Design and related documentation. Spartan-6 FPGA Embedded Kit Documentation

Upgrading to the Spartan-6 FPGA Connectivity Kit


This is for users who currently have any of the following Spartan-6 kits:
  • Spartan-6 FPGA SP605 Evaluation Kit
  • Spartan-6 FPGA Embedded Kit

Please visit http://www.xilinx.com/products/boards_kits/upgrade.htm for further details.

Archived Files - ISE Design Suite 11.4

 
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