Virtex-6 FPGA Connectivity Kit Reference Design and Documentation

The Virtex®-6 FPGA Connectivity Kit enables faster design development and provides a jump-start through the connectivity targeted reference design included in it.

Note: For information on upgrading from the Virtex-6 FPGA ML605 Evaluation Kit or other domain-specific Virtex-6 design platform, see the specific steps at the bottom of this page.

Reference Design & Documentation	ISE® Design Suite 13.4	ISE Design Suite 13.2
Virtex-6 LXT FPGA Connectivity Targeted Reference Design
Supporting AXI4 Interconnect standard: This is a x4PCIeGen2-DMA-DDR3-XAUI design supporting AXI4 interconnect standard, that simplifies designing with the main integrated components in a Virtex®-6 FPGA. The Integrated Endpoint Block for PCI Express® and GTX transceivers work together in an application with additional IP cores, such as a Northwest Logic Packet DMA engine for the PCI Express interface, XAUI LogiCORE™ IP, and Memory Interface Generator (MIG) tool.	Virtex-6 LXT FPGA: Production Silicon (Reference Design & Documentation - AXI4 Support) (zip)	Virtex-6 LXT FPGA: Production Silicon (Reference Design & Documentation - AXI4 Support) (zip) AXI4 support Windows Device Drivers and Application support
Supporting Legacy Interfaces: This is a x4PCIeGen2-DMA-DDR3-XAUI design that simplifies designing with the main integrated components in a Virtex-6 FPGA. The Integrated Endpoint Block for PCI Express and GTX transceivers work together in an application with additional IP cores, such as a Northwest Logic Packet DMA engine for the PCI Express interface, XAUI LogiCORE IP, and Memory Interface Generator (MIG) tool.	Not supported for IDS 13.4 Pl. use the design supported in the IDS 12.4 Design Tools.	Not supported for IDS 13.2 Pl. use the design supported in the IDS 12.4 Design Tools.
Virtex-6 FPGA Connectivity Kit Hardware Setup Guide
The Virtex-6 FPGA Connectivity Kit Hardware Setup Guide provides a step by step hardware setup and overview of the Kit.	Hardware setup guide (pdf)	Hardware setup guide (pdf)
Virtex-6 FPGA Connectivity Kit Getting Started Guide
The Virtex-6 FPGA Connectivity Kit Getting Started Guide provides hardware setup steps and step by step overview of the Connectivity Targeted Reference Design. It covers the steps for the Installation of the Software as well as where to find additional resources.	Virtex-6 FPGA Connectivity Kit Getting Started Guide (pdf)	ug664 (v1.4) (pdf)
Virtex-6 FPGA Connectivity Kit Reference Design User Guide
Supporting AXI4 Interconnect standard: The Virtex-6 FPGA Connectivity Targeted Reference Design is a fully scalable PCIe to XAUI bridge that provides an efficient platform for accelerating system design development in a Virtex-6 FPGA device. GTX transceivers Endpoint Block for PCIe, supporting AXI4 Interconnect standard Bus Mastering PCIe Packet DMA engine from Northwest Logic, supporting AXI4 Interconnect standard (optimized for Virtex-6 FPGA) Xilinx 10 Gigabit Attachment Unit Interface (XAUI) Logicore IP	Virtex-6 FPGA Connectivity Targeted Reference Design with AXI4 Protocol User Guide (pdf)	ug379 (v1.3) (pdf)
Supporting Legacy Interfaces: The Virtex-6 FPGA Connectivity Targeted Reference Design is a fully scalable PCIe to XAUI bridge that provides an efficient platform for accelerating system design development in a Virtex-6 FPGA device. GTX transceivers Endpoint Block for PCIe Bus Mastering PCIe Packet DMA engine from Northwest Logic (optimized for Virtex-6 FPGA) Xilinx 10 Gigabit Attachment Unit Interface (XAUI) Logicore IP	Not supported for IDS 13.4 Pl. use the documentation with the design supported in the IDS 12.4 Design Tools.	Not supported for IDS 13.2 Pl. use the documentation with the design supported in the IDS 12.4 Design Tools.
Additional Documentation
This includes ML605 FPGA Board User Guide, Schematics, PCB files as well as other base reference designs like IBERT and BIST designs.	Virtex-6 FPGA Evaluation Kit Documentation
This includes Embedded Targeted Reference designs including Microblaze® Processor Sub-system Design and related documentation.	Virtex-6 FPGA Embedded Kit Documentation

Upgrading to the Virtex-6 FPGA Connectivity Kit

This is for users who currently have any of the following Virtex-6 kits:

Virtex-6 FPGA ML605 Evaluation Kit
Virtex-6 FPGA Embedded Kit
Virtex-6 FPGA DSP Kit

Upgrading to the equivalent of the Virtex-6 FPGA Connectivity Kit is performed by the following steps:

Download the Connectivity Targeted Reference Design from the link at the top of this page.
Purchase the Embedded Development Kit (EDK) or download an evaluation, if not already available on your computer
Purchase the FMC XM104 Connectivity Card
Purchase the CX4 Loopback connector
Program the ML605 Board (Platform Flash) with the Connectivity Targeted Reference Design from the Reference Design ZIP file
Contact your Xilinx FAE to get access to Fedora 10 Live CD (Linux OS)

Archived Files

- ISE Design Suite 12.4