The Vivado™ Design Suite accelerates the implementation process by delivering more turns per day while helping to eliminate them altogether. A revolutionary shared scalable data model delivers up to 4X faster run times and half the memory footprint of competing solutions.
Note: The graph above highlights both the run time advantage and the predictable behavior of the Vivado place and route engine. Run times are consistently up to 4x faster than alternative solutions while the variance in results is much tighter enabling design closure with fewer iterations.
Vivado Synthesis is a timing driven synthesis tool that supports VHDL, Verilog and SystemVerilog. The tool is also compatible with Synopsys Design Constraints (SDC). Built to scale for the largest designs, it also delivers fast runtimes for improved productivity. Vivado Synthesis integrates tightly into the Vivado Integrated Design Environment (IDE) and allows for cross-probing to the RTL and technology view (device view) as well as source. The Vivado Static Timing Analyzer can directly time the synthesis results and paths of interest can be selected to cross-probe directly to any open views in Vivado IDE, providing an unparalleled design environment for analysis and debug.
The Vivado Design Suite offers push button power reduction using proven ASIC technology for FPGA. This technology saves up to 30% dynamic power by automatically turning off unused portions of the design. Designers can use this fine-grained clock gating technology without requiring device architecture expertise allowing Vivado to optimize the entire design for power savings or provide directives to optimize only portions of the design through simple constraints.
The Vivado Design Suite provides an integrated state of the industry analytical place-and-route technology that provides the advantage of finding an optimal implementation based on multi-variable cost function.
Analytical place-and-route reduces the placement solution space into a large equation and uses an analytical solver to find a placement that minimizes a given cost function. Vivado uses a multi-variable cost function, based on timing, wire length and congestion metrics. Optimizing for this cost function allows for quickly finding a routable solution that maximizes performance while minimizing dynamic power.
Using the Vivado device editor make ECO changes such as move instances, reroute nets, tap a register to a primary output for debug with scope, change the parameters on a Digital Clock Manager (DCM) or a Look-Up Table (LUT) late in the design cycle without the need to rerun synthesis and implementation.
The Vivado’s incremental flow allow for ECOs to be quickly processed by only re-implementing a small part of the design, while preserving performance. No other design environment offers this level of flexibility, enabling performance preservation after each incremental change, reducing the need for multiple design iterations.