Vivado High-Level Synthesis
Advanced algorithms used today in wireless, medical, defense, and consumer applications are more sophisticated than ever before. Vivado® Design Suite, Vivado High-Level Synthesis accelerates IP creation by enabling C, C++ and System C specifications to be directly targeted into Xilinx All Programmable devices without the need to manually create RTL. Supporting both the ISE® and Vivado design environments Vivado HLS provides system and design architects alike with a faster path to IP creation by :
- Abstraction of algorithmic description, data type specification (integer, fixed-point or floating-point) and interfaces (FIFO, AXI4, AXI4-Lite, AXI4-Stream)
- Directives driven architecture-aware synthesis that delivers the best possible QoR
- Fast time to QoR that rivals hand-coded RTL
- Accelerated verification using C/C++ test bench simulation, automatic VHDL or Verilog simulation and test bench generation
- Multi-language support and the broadest language coverage in the industry
- Automatic use of Xilinx on-chip memories, DSP elements and floating-point library
All 7 Series, Zynq®-7000 and UltraScale™ devices. Support older architectures as well for with ISE (*).
Vivado High-Level Synthesis is available stand alone or as part of the Vivado Design Suite System Edition.
Key Documents
For the most current links to Vivado High-Level Synthesis resources, use the Design Hub View in Vivado Document Navigator and select "High-Level Synthesis".
| Name | Description |
|---|---|
| WP416 Vivado Design Suite | Vivado Design Suite Backgrounder |
| UG871Vivado Design Suite Tutorial | High-Level Synthesis |
| UG902 Vivado Design Suite User Guide | High-Level Synthesis |
| UG958 Vivado Design Suite Reference Guide | Model-based DSP Design using System Generator |
Application Notes
| XAPP599 | Floating Point Design with Vivado HLS |
| XAPP745 | Processor Control of Vivado HLS Designs |
| XAPP793 | Implementing Memory Structures for Video Processing |
| XAPP890 | Zynq All Programmable SoC Sobel Filter Implementation |
| XAPP1167 | Accelerating OpenCV Applications with Zynq-7000 AP SoC using Vivado HLS Video Libraries |
(*): Via additional license or with ISE Design Suite - System Edition.
