Quickly simulate, analyze and modify the design without being distracted with implementation details. By starting with untimed C/C++/System C or MATLAB™/Simulink™.
Advanced algorithms used today in wireless, medical, defense, and consumer applications are more sophisticated than ever before. Vivado™ Design Suite, Vivado High-Level Synthesis accelerates IP creation by enabling C, C++ and System C specifications to be directly targeted into Xilinx All Programmable devices without the need to manually create RTL. Supporting both the ISE® and Vivado design environments Vivado HLS provides system and design architects alike with a faster path to IP creation by :
With System Generator for DSP, create production-quality DSP algorithms in a fraction of time compared to traditional RTL.
Supporting both the ISE® and Vivado design environments System Generator accelerates the development of highly parallel systems with the industry’s most advanced All Programmable system modeling and automatic code generation from Simulink™ and MATLAB™ (The MathWorks, Inc.)
Kintex™-7, Virtex®-7, Zynq™-7000, Virtex-6, Virtex-5, Virtex-4,Virtex-II Pro, Virtex-II, Spartan®-6, Spartan-3
Both Vivado High-Level Synthesis and System Generator for DSP are available stand alone or as part of the ISE® Design Suite DSP and System Editions and Vivado Design Suite System Edition.
|Vivado High-Level Synthesis License||Supported devices||RTL synthesis to Bitstream Implementation Flow|
|Included with Vivado System Edition (HLS feature)||
|Standalone Vivado High-Level Synthesis (Vivado_HLS feature)||7 Series||Vivado, ISE|
|Zynq, Virtex-6, Virtex-4, Virtex-5, Spartan-6, Spartan-3||ISE|