Quickly simulate, analyze and modify the design without being distracted with implementation details. By starting with untimed C/C++/System C or MATLAB™/Simulink™.

Advanced algorithms used today in wireless, medical, defense, and consumer applications are more sophisticated than ever before. Vivado™ Design Suite, Vivado High-Level Synthesis accelerates IP creation by enabling C, C++ and System C specifications to be directly targeted into Xilinx All Programmable devices without the need to manually create RTL. Supporting both the ISE® and Vivado design environments Vivado HLS provides system and design architects alike with a faster path to IP creation by :

• Abstraction of algorithmic description, data type specification (integer, fixed-point or floating-point) and interfaces (FIFO, AXI4, AXI4-Lite, AXI4-Stream)
• Directives driven architecture-aware synthesis that delivers the best possible QoR
• Fast time to QoR that rivals hand-coded RTL
• Accelerated verification using C/C++ test bench simulation, automatic VHDL or Verilog simulation and tes tbench generation
• Multi-language support and the broadest language coverage in the industry
• Automatic use of Xilinx on-chip memories, DSP elements and floating-point library
• Generating project as a Pcore for Xilinx Platform Studio, block for use in System Generator for DSP or IP for use from the Vivado IP catalog

With System Generator for DSP, create production-quality DSP algorithms in a fraction of time compared to traditional RTL.

Supporting both the ISE® and Vivado design environments System Generator accelerates the development of highly parallel systems with the industry’s most advanced All Programmable system modeling and automatic code generation from Simulink™ and MATLAB™ (The MathWorks, Inc.)

• Integrate RTL, embedded IP, MATLAB, and hardware components of a DSP system
• Part of the Xilinx DSP Targeted Design Platform integrated with the Vivado™ integrated design environment, IP catalog and High-Level Synthesis
• Bit and cycle accurate floating and fixed-point implementation
• Automatic code generation of VHDL or Verilog from Simulink
• Accelerated modeling and verification using Hardware and HDL co-simulation
• Hardware / software co-design of embedded systems

Comprehensive Device Support

Kintex™-7, Virtex®-7, Zynq™-7000, Virtex-6, Virtex-5, Virtex-4,Virtex-II Pro, Virtex-II, Spartan®-6, Spartan-3

Both Vivado High-Level Synthesis and System Generator for DSP are available stand alone or as part of the ISE® Design Suite DSP and System Editions and Vivado Design Suite System Edition.