^

Accelerating Integration

Block-based IP Integration with Vivado IP Integrator

The Vivado® Design Suite shatters the RTL design productivity plateau by providing the industry’s first plug-and-play IP integration design environment, with its IP Integrator feature.

Vivado IP Integrator provides a graphical and Tcl-based, correct-by-construction design development flow. It provides a device and platform aware, interactive environment that supports intelligent auto-connection of key IP interfaces, one-click IP subsystem generation, real-time DRCs, and interface change propagation, combined with a powerful debug capability.

Designers work at the “interface” and not “signal” level of abstraction when making connections between IP, greatly increasing productivity.  Often times this is using industry standard AXI4 interfaces, but dozens of other interfaces are also supported by IP integrator.

Working at the interface level, design teams can rapidly assemble complex systems that leverages IP created with Vivado HLS, System Generator, Xilinx SmartCore™ and LogiCORE™ IP, Alliance Member IP as well as your own IP. By leveraging the combination of Vivado IPI and HLS customers are saving up to 15X in development costs versus an RTL approach.

Vivado IP Integrator benefits include:

  • Tight integration within the Vivado Integrated Design Environment
    • Seamless inclusion of IPI hierarchical subsystems into the overall design
    • Rapid capture and packaging of IPI designs for reuse
    • Support for both graphical and Tcl-based design flows design
    • Rapid simulation and cross-probing between multiple design views
  • Support for all design domains
    • Support for processor or processor-less designs
    • Integration of algorithmic (Vivado HLS and System Generator) and RTL-level IP
    • Combination of DSP, video, analog, embedded, connectivity, and logic
  • Focused on Designer Productivity
    • DRCs on complex interface level connections during design assembly
    • Recognition and correction of common design errors
    • Automatic IP parameter propagation to interconnected IP
    • System-level optimizations
    • Automated designer assistance

C-based IP Generation with Vivado High-Level & Synthesis Model-based DSP Design Integration with System Generator for DSP

As the leading provider of Electronic System Level Design tools for All Programmable solutions, Vivado Design Suite System Edition provides Vivado High-Level Synthesis for C, C++ and SystemC, and MATLAB™/Simulink™ based System Generator for DSP. These solutions enable high-level IP specifications to be directly synthesized into VHDL and Verilog accelerating IP verification over 100X and RTL creation by up to 4X. The highly integrated tools can be used individually or in combination with the result being reusable IP for use in the Vivado Design Suite.