Accelerating the development of smarter systems requires levels of automation that go beyond RTL level design. With the introduction of the Vivado™ Design Suite, Xilinx delivers a SoC-strength, IP-and system centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation.
Accelerated design integration is achieved through a new IP-centric design flow that quickly turns a user’s design or algorithms into reusable IP.
To accelerate the creation of highly integrated, complex designs in All Programmable devices, Vivado Design Suite 2013.1 is delivering intelligent IP integration with an early access release of the new IPI feature which provides a new graphical and TCL based, correct-by-construction, IP- and system centric design development flow.
Built on the foundation of Vivado, the IPI feature provides a device and platform aware, interactive environment that supports intelligent auto-connection of key IP interfaces, one-click IP subsystem generation, real-time DRCs, and interface change propagation, combined with a powerful debug capability.
Working at the interface level, design teams can rapidly assemble complex systems and leverage Vivado to ensure designs and IP are configured correctly. IPI’s built in automated interface, device driver, and address map generation speeds design assembly. Getting from concept to debug has never been faster.
To request an early access license, please contact your local sales representatives.
The Vivado IP packager is a unique design reuse feature based on an IP-XACT, that provides the ability to package a core at any stage of the design flow. Users can package their own RTL, or C/C++/SystemC and MATLAB®/Simulink® algorithms into the IP catalog using Vivado High-Level Synthesis (HLS) or System Generator for DSP.
The IP Packager enables Xilinx, designers and 3rd party IP providers to package a core complete with constraints, test benches and documentation and made available in the IP catalog, as well as on a local or shared drive for enterprise use. With customized parameterization GUI for easy instantiation and support for secure delivery of encrypted IEEE P1735 design files the IP Packager facilitates design reuse at the enterprise level.
The Vivado IP Catalog provides a repository for Xilinx IP including embedded, DSP, connectivity, building block and interconnect IP, 3rd party and intra-company IP that can be shared across a design team, division or company in a manner that facilitates design reuse. Support for multiple physical locations: including shared networked drives allows users or organizations to leverage a consistent IP deployment environment for 3rd party or internally generated IP.