UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Vivado Simulation Flow

The Vivado® Design Suite provides an array of design entry, timing analysis, hardware debug, and simulation capabilities all encompassed in a single state of the art integrated design environment (IDE). This flow enables both the integrated and enterprise verification needs for all supported simulators.

Vivado enables behavioral, post-synthesis and post-implementation (functional or timing) simulations for the fully integrated Vivado Simulator and 3rd party HDL simulators. Time spent on simulation early in the design cycle helps identify issues early and significantly reduces turnaround times compared to later stages of the flow.

To aid flexibility in user verification environments, Vivado provides support for both an integrated environment as well as provides scripts to use with external verification setups.

What’s New in Vivado Design Suite 2016.3

Simulation Flow

  • Complete support for the enterprise user environment with non-project based flow.
  • Consistently supported in all  Vivado environments (IP, RTL and IP Integrator)
  • IP generation step creates simulation scripts for all supported simulators
  • Advanced ability to generate scripts for simulator of choice on per IP basis.
  • Intelligent compilation significantly reduces disk space and compilation time, by re-using existing IP compilation.


Simulation Performance

The Vivado IDE supports all major simulators in integrated mode for interactive simulation users and script mode for advanced verification engineers.

Vendor Simulators Interactive Scripts
Aldec Active-HDL, Riviera-PRO
Cadence Incisive Enterprise Simulator (IES)
Mentor Graphics ModelSim, Questa Advanced Simulator
Synopsys VCS
Xilinx Vivado Simulator

Feature highlights:

  • Vivado provides the ability to compile simulation libraries for the supported simulators in the users’ environment to enable re-use of compiled libraries.
  • Ability to simulate and verify design integrity at different stages of the design process
    • Behavioral simulation
    • Post-synthesis functional and  timing simulation
    • Post-implementation functional and timing simulation
  • Portable integrated simulation environment
    • Unified simulation integration  using consistent 3 step process (compile, elaborate, simulate) for all simulators
  • Simulation script generation for enterprise 3rd party simulators
    • IP generation step creates simulation scripts
    • Users enabled with generation of scripts to incorporate into user environments

The Vivado integrated design environment (IDE) provides users with the ability to explore multiple simulation strategies using simulation sets. The simulation sets allows users to manage the verification process within the Vivado IDE and creates different simulation flows depending on the verification needs.

The Vivado integrated design environment (IDE) provides users with the ability to explore multiple simulation strategies using simulation sets. The simulation sets allows users to manage the verification process within the Vivado IDE and creates different simulation flows depending on the verification needs.

Feature highlights:

  • Flexible simulation environment to explore different simulation strategies
    • Different Verilog defines
    • Change sources (testbench, header files…)
  • Compare multiple simulations – side by side
    • Run behavioral and post-synthesis simulation simultaneously
  • Organize simulation flows
    • Separate simulation sets can be created for module level simulation and system level simulation

Key Documents

QuickTake Video Tutorials

Name Duration Release Date
Simulating with Mentor Questa in Vivado 06:23 min 04/28/2015
Simulating with Cadence IES in Vivado 07:00 min 04/28/2015
Simulating with Synopsys VCS in Vivado 06:03 min 04/28/2015
Using Vivado Logic Simulator for Multiple Sim Sets 06:57 min 10/04/2012