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Vivado Design Suite 2017.1 Tips and Tricks

Tip#1

RPX files are binary files that enable you to create reports from a Tcl command and view the results in the graphical environment. The report commands that support this interface include:  report_drc, report_methodology, report_power, report_timing, report_timing_summary, and report_utilization. To create the binary report, you can issue each of these Tcl commands with a –rpx <filename> option. When you open the design checkpoint in the graphical environment, you can access the report from by choosing File > Open Interactive Report. This mechanism is used by the project flow to restore all the reports when you open an implemented design.

Tip#2

For the first time in Vivado v2017.1, RTL synthesis allows you to assign specific synthesis options to instances of your design. This is done through the new block_synth XDC property, it allows you to tune a design by optimizing differently various parts of your design: for example, a timing critical instance could be retimed while less timing critical instances could be optimized for area. No changes to the RTL or design setup are required, all can be done through XDC.

Tip#3:

Waveform viewer in Vivado simulator allows you to search for values. You can right click on the signal in waveform viewer and select find value or alternatively you can use Ctrl+Shift+F.

Tip#4:

Vivado now supports IP encryption based on IEEE 1735-2014 standard? Please watch this Quick Take Video to learn about IP encryption flow in Vivado and how to prepare IPs for encryption.

Tip#5:

The export_simulation command makes it a lot easier to run simulation in batch or script mode? This command collects all design files required for simulation and generates simulation script for the top-level RTL design or sub-design. The most important part is that it will generate script for all supported third-party simulator.