Vivado enables users to accelerate design productivity by providing key debug and programming features that architected for current as well as future Xilinx FPGA device families. These features are tightly integrated with Vivado™ design environment, including Vivado logic analyzer, Vivado serial I/O analyzer, and Vivado device programmer.

Vivado Logic Analyzer

Key Features

• Integrated into Vivado environment
  • IDE integration
  • All debug cores available via the IP Catalog
  • One-click enablement in IP Integrator
• HDL (VHDL,Verilog) based core instantiation and Synthesized Netlist based core insertion
• Analyze any internal FPGA signal, including embedded processor system buses
• High-level debug with flexible probing capability
• Debug remotely over a network connection
  
  

Support Device Families

• Artix™-7 FPGAs, Zynq™-7000 All Programmable SoC, Kintex™-7 FGPAs (All); Virtex®-7 series FPGAs (All)

Vivado Serial I/O Analyzer

The Vivado serial I/O analyzer provides a fast, easy, and interactive setup and debug of serial I/O channels in high-speed FPGA designs. The serial I/O analyzer allows you to take bit-error ratio (BER) measurements on multiple channels and adjust high-speed serial transceiver parameters in real-time while your serial I/O channels interact with the rest of the system.

Key Features

• New RX Margin Analysis tool takes advantage of the Eye Scan feature in 7 Series FPGA transceivers
  • 2D Full Scan: Scans all horizontal and vertical offset sampling points within the “eye”
  • 1D Bathtub: Scans all horizontal sampling points through the 0 vertical row offset
• Fast and easy interactive setup and debug of FPGA serial I/O channels
• Measure bit-error ratios (BER) on multiple channels simultaneously
• Adjust high-speed serial transceiver parameters in real-time while your serial I/O channels are interacting with the rest of the system
• Built-in pattern generators and checkers, including many standard ITU standard patterns
• Requires only JTAG port access to your board, no extra pins needed for dedicated high-speed serial debug or setup 

• Artix-7 FPGAs, Zynq-7000 All Programmable SoC, Kintex-7 FGPAs (All); Virtex-7 series FPGAs (All)

Vivado Device Programmer

The Vivado device programmer enables you to program and configure Xilinx FPGA devices.

Key Features

• GUI and TCK script support   
  • Enable cable sharing between different applications
  • Software Development Kit, System Generator, and Vivado Analyzer can share a single cable
  • Requires Digilent HS1/SMT1 and HS2/SMT2 USE-based JTAG Cables
  • Cable solution built using the Target Communication Framework (TCF) network protocol
• Direct FPGA Programming - program FPGA bitstreams directly through JTAG
  
  

Vivado Simulator

The Vivado simulator is a Hardware Description Language (HDL) event driven simulator that supports functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog designs. Vivado Simulator integrates tightly into the Vivado IDE allowing users to do waveform tracing and debug with the push of a button. With a 3X performance advantage, Vivado simulator allows more turns per day for designers by offering multithreaded compilation and simulation optimizations.

• Mixed language support
• Supports VHDL-93 and Verilog 2001
• Analog Waveform Viewer
• Native support for all HardIP blocks
• No special license requirements
• Supports AXI Bus Functional Model (BFM)
• Multi-Threaded compilation
• Post-Processing capabilities
• Tcl scriptable GUI and batch mode simulation run
• Waveform tracing, waveform viewing, HDL source debugging
• Power Analysis and optimization using SAIF
• Easy to use - One-click compilation and simulation
• Built in Xilinx simulation libraries including hard IP
• Additional mapping or compilation not required