The ISE® Design Suite includes Xilinx Synthesis Technology (XST) allowing synthesis of HDL designs to create Xilinx specific netlist files. With specially optimized algorithms to leverage the advanced architectures of the Xilinx FPGA families, XST offers designers a low-cost design solution to achieve optimal design results.
Integrated within the ISE Project Navigator, XST provides support for mixed-language Verilog and VHDL designs. This flexibility allows designers to mix the best possible design source code for any particular project. This, in turn, allows you to more easily and quickly mix and match your purchased IP with your own in-house design expertise regardless of design language.
XST helps designers solve their toughest design challenges:
- Performance - XST incorporates next-generation physical synthesis optimizations through techniques such as register balancing, global optimization, timing-driven synthesis, and logic optimization to improve the quality of results.
- Reduced Runtime and Design Preservation - With its tight integration within the ISE SmartCompile™ Technology, XST helps maintain successful results to dramatically reduce runtimes during subsequent re-implementations.
- Power Reduction - Power optimizations in XST provide power-aware logic optimizations for macro processing on blocks such as multipliers, adders and BRAMs
- Ease-of-use - XST provides designers with additional features to better explore their synthesis results. Integrated RTL and Technology Viewers allow designers to view their RTL netlist to better visualize how XST inferred the components of their design to help identify problems and improve their design early in the process.
IEEE HDL Standards Compliant
- VHDL: IEEE 1076-1993
- Verilog: IEEE 1364-2001