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ISP Standards & Specifications

In-system Programmability (ISP) Standards and Specifications:

IEEE Std 1149.1 Background

The Boundary Scan/JTAG, formally known as IEEE/ANSI standard 1149.1_1190, is a set of design rules which facilitate the testing, device programming and debug at chip, board, and systems levels. The standard was developed by the Joint Test Action Group (JTAG) formed by several North American and European companies. IEEE Std 1149.1 was originally developed as an on-chip test infrastructure capable of extending the lifetime of available automatic test equipment (ATE). Extensive information can be found on the Texas Instruments Boundary Scan Page. Incorporating design-for-test using this standard allows complete control and access to the boundary pins of a device without a bed-of -nails or other test equipment. Each JTAG compliant device includes a boundary cell on the input/output pins (Figure 1). Under normal conditions, it is transparent and inactive, allowing signals to pass normally.With the device in test mode, you can capture input signals for later analysis and output signals can be set to affect other devices on the board.

Boundary Scan Cell Diagram

Simply stated, the IEEE Std 1449.1 defines a serial protocol that requires 4 (optionally 5) pins on each compliant device, regardless of the packaging constraints. These pins define a Test Access Port (TAP) to enable operation of the on-chip test infrastructure that ensures:

  • All components on a printed circuit board are mounted properly and in the right place.
  • All interconnections between components are as described in the design.

The pins are:

  • TCK - a clock signal that synchronizes the 1149.1 internal state machine operations.
  • TMS - the 1149.1 internal state machine mode select signal. This signal is sampled at the rising edge of TCK to determine the next state machine state.
  • TDI - the 1149.1 data input pin. When the internal state machine is in the correct state, this signal is sampled at the rising edge of TCK and shifted into the device's test or programming logic.
  • TDO - the 1149.1 data output pin. When the internal state machine is in the correct state, this signal represents the data shifted out of the device's test or programming logic. The output data is valid on the falling edge of TCK.
  • TRST (optional) - the 1149.1 asynchronous reset pin. When driven low, the internal state machine advances immediately to the reset state. Since the pin is optional and pins are generally high cost additions to devices, it is infrequently used. In addition, the internal state machine (as defined by the standard) has a well defined synchronous reset mechanism.

The TAP pins drive a 16-state controller (state machine). The state machine transitions between states according to the value of the TMS signal value on the rising edge of TCK. View the state machine illustration in the answer database.

The `0' and `1' along the transition arcs represents the state of the TMS signal at the rising edge of TCK.

The 1149.1 standard defines that TDI is valid and shifted in (and TDO valid and shifted out) only in the Shift-DR or Shift-IR states. The Shift-IR state selects the device instruction register between TDI and TDO. Depending on the instruction selected different data registers are activated. When in Shift-DR, the data register appropriate for the previously entered instruction is selected between TDI and TDO. The default data register is the mandatory 1-bit bypass register.

An external Boundary-Scan Description Language (BSDL) file defines the properties and characteristics of any single device's boundary-scan logic. These files, supplied by the IC manufacturer, are used in the generation of any algorithmic description of the operation of the IEEE 1149.1 compliant device.

Multiple boundary-scan devices are serially connected in a daisy chain. Each device shares the same TCK and TMS. The TDO of one device links to the TDI of the next. Since all devices share the same TCK and TMS, all devices sequence through the TAP controller synchronously and concurrently. Consequently, all devices are simultaneously in the same TAP controller state. When shifting data (in the Shift-IR or Shift-DR state) into the boundary-scan chain, all devices have registers internally linked between their TDI and TDO pins. The apparent result is a single fixed-length shift register from the system TDI pin to the system TDO.

IEEE Std 1532 Configuration and Programming Standard

Newly designed systems utilizing state-of-the-art PLDs and configuration PROMs demand the best programming and configuration techniques. The IEEE Std 1532 specification enables designers to concurrently program multiple devices, minimize programming times with enhanced silicon features, and produce robust systems that are more easily maintained. This new standard paves the way for easy hardware upgrades by providing a robust and reliable programming environment.

The IEEE Std 1532 specification simplifies the configuration of any conforming PLD, even in a remote environment. Its unified approach to programming virtually eliminates any device programming uncertainties and guarantees orderly system startup, even after power failure. It allows users to easily implement field diagnostics and new features to extend product life cycles and lower field maintenance costs.

IEEE 1532

Programming and algorithm data are kept separate. Either can be changed without affecting the other, eliminating the need to recompile after every design change. Boundary scan tools and automatic test equipment can maximize programming efficiency and minimize programming times, lowering production costs.

IEEE Std 1532 features well defined system level instructions that make enhancements like concurrent programming simple to implement further reducing programming times. By using these simplified instructions, designers can reduce time to market and focus their attention on system features and design optimization rather than configuration concerns.

Device and Software Support

The following devices and series of products can take full advantage of the IEEE 1532 Std specification (see IEEE Std 1532 BSDL files):

  • CoolRunner™-II CPLDs
  • Spartan® series FPGAs
  • Virtex® series FPGAs
  • System ACE™

Xilinx also offers the world's first IEEE Std 1532 programming engine J Drive as a free download.

Automatic Test Equipment (ATE), 3rd Party Tool and In Line Programmer Participants

Major telecommunications and consumer electronics companies cooperated to establish the standard met their needs across a wide variety of different programmable devices. Major Automatic Test Equipment manufacturers (Agilent and Teradyne), Boundary Scan tool suppliers (ASSET Intertech, Corelis, Intellitech, and JTAG Technologies) and in-line programmer suppliers (Data I/O and BP Microsystems) participated in the development of IEEE-STD-1532.

We provide a list of ATE and Boundary Scan (JTAG) Tools and Partners for your convenience.

Serial Vector Format (SVF)

Serial Vector Format (SVF) Specification is the de facto standard for interchange of boundary scan based stimulus information. While it is freely distributed, it is not an open standard. It is currently copyrighted and controlled by Asset Intertech.

JEDEC

  • The JEDEC Programming File is more formally known as the JESD3-C Standard Data Transfer Format Between Data Preparation System and Programmable Logic Device Programmer. You can download this file from the JEDEC site.
  • The JEDEC Chain Description File is more formally known as the JESD32 Standard for Chain Description File. This file format describes the connection of arbitrary programmable devices in a serial chain. It attempts to balance a description of both non-1149.1 and 1149.1 types of serial chains in the same language. However, it is unable to describe complex boundary scan chain configurations such as hierarchical or multidrop architectures.

BSDL

Boundary Scan Description Language (BSDL) Standard 1149.lb describes the 1149.1 TAP controller and boundary scan register on a JTAG 1149.1 boundary scan compliant device. BSDL is also implemented as a subset of the VHDL standard. Xilinx extensively tests and verifies each BSDL File.

 
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