Configuration for Spartan-3A/3E FPGAs

Solutions and resources for configuring Spartan-3A and Spartan-3E FPGAs

Spartan™-3A/3E FPGAs use CMOS Configuration Latches (CCLs) to enable configurable interconnects between routing lines and logic cells. Spartan-3A/3E FPGAs are volatile devices - they do not retain their configuration when power is removed. To configure a Spartan-3A/3E FPGA, you must reinitialize the CCLs inside the FPGA each time power is cycled. Power-up configuration for Spartan-3A/3E FPGAs varies by application. For more details, select a link below:

Prototyping or Debugging

Customers who are in the prototyping phase have the following options for the Spartan-3A/3E FPGA configuration:

• Xilinx JTAG Programming Cable
  Xilinx provides low cost JTAG cables that can be used to directly configure a Spartan-3A/3E FPGA in the prototyping environment, without a non-volatile memory source. Xilinx JTAG cables are fully supported by iMPACT software, which is a part of the ISE™ software.
  
  
• Third Party Cables/Solutions
  Xilinx also works with third party vendors to provide Boundary Scan (JTAG) tools that can be used in prototyping environments, without the need for a non-volatile memory source.

In the Field

In the field, customers must implement a non-volatile configuration memory solution to configure Spartan-3A/3E FPGAs. Xilinx offers the following options:

• Platform Flash
  Platform Flash is the simplest and most cost effective configuration memory solution for Spartan-3A/3E FPGAs. Platform Flash is a Xilinx proprietary, single-chip, drop-in solution that is offered in densities ranging from 1-Mb up to 32-Mb.
  
  
• Processor Controlled
  Customers who have an onboard processor may opt to use it to configure Spartan-3A/3E FPGAs a non-volatile memory solution is still required. The following application notes provide details on how to implement a processor controlled configuration solution.
  • XAPP058 (PDF): Compact JTAG-based configuration method for all Xilinx ISP devices
    
  • XAPP500 (PDF): IEEE STD 1532 (JTAG-based) configuration method for all 1532-compliant devices
    
  • XAPP502 (PDF): Compact method for Xilinx slave-serial or slave-SelectMAP configuration modes
    
  • XAPP441 (PDF): Remote FPGA reconfiguration using MicroBlaze™ or PowerPC™
    
    
• Standard Flash Memory
  Spartan-3A/3E FPGAs are the industry’s first and only FPGA that provides direct open configuration memory interface. These devices are compatible with most industry standard Flash memories. The following application notes provide support beyond compatibility.
  • XAPP951 (PDF): Configuring Xilinx FPGAs with Serial Flash

Miscellaneous

• Spartan-3A FPGAs
• Spartan-3E FPGAs
• Spartan-3 Generation Configuration User Guide
• XAPP693 (PDF): A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs
  
• System ACE™ CF

Configuration Schemes

Xilinx offers the end user flexibility when configuring a Spartan-3A/3E FPGA. The following schemes are supported by Spartan-3A/3E FPGAs:

Serial

Simplest configuration scheme, serial throughput.

Master Serial

The Xilinx FPGA drives the Xilinx PROM CLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Slave Serial with Internal Oscillators

The Xilinx PROM’s internal oscillator drives the Xilinx FPGA CCLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Slave Serial with External Clock Driving PROM only

An external clock drives the Xilinx PROM CLK and the Xilinx PROM drives the Xilinx FPGA CCLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Slave Serial with External Clock Driving FPGA and PROM

An external clock drives both the Xilinx FPGA CLK and the Xilinx PROM CLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Master SPI

The Spartan-3A/3E FPGA drives the SPI PROM Clock as the SPI PROM provides serial (x1) configuration data to the Spartan-3A/3E FPGA.

Parallel

Parallel configuration for fastest throughput.

Master Parallel

The Xilinx FPGA drives the Xilinx PROM CLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

The Master Parallel configuration method is enabled through the Spartan-3A/3E FPGA BPI configuration setting.

Slave Parallel with Internal Oscillator

The Xilinx PROM’s internal oscillator drives the Xilinx FPGA CCLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

Slave Parallel with External Clock Driving PROM only

An external clock drives the Xilinx PROM CLK and the Xilinx PROM drives the Xilinx FPGA CCLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

Slave Parallel with External Clock Driving FPGA and PROM

An external clock drives both the Xilinx FPGA CCLK and the Xilinx PROM CLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

Master BPI

The Spartan-3A/3E FPGA drives the Parallel Flash PROM as the Parallel Flash PROM provides byte-wide (x8) configuration data to the Spartan-3A/3E FPGA.