Configuration for Virtex-4 FPGA

Solutions and resources for configuring Virtex-4 FPGAs

Virtex™-4 FPGAs use CMOS Configuration Latches (CCLs) to enable configurable interconnects between routing lines and logic cells. Virtex-4 FPGAs are volatile devices - they do not retain their configuration when power is removed. To configure a Virtex-4 FPGA, you must reinitialize the CCLs inside the device each time power is cycled. Power up configuration for Virtex-4 FPGAs varies by application.

Prototyping or Debugging

Customers who are in the prototyping phase have the following options for Virtex-4 FPGA configuration:

• Xilinx JTAG Programming Cable
  Xilinx provides low cost JTAG cables that can be used to directly configure a Virtex-4 FPGA in the prototyping environment, without a non-volatile memory source. Xilinx JTAG cables are fully supported by iMPACT software, which is a part of the ISE software.
  
  
• Third Party Cables/Solutions
  Xilinx also works with 3rd party vendors to provide Boundary Scan (JTAG) tools that can be used in prototyping environments, without the need for a non-volatile memory source.

In the Field

In the field, customers must implement a non-volatile configuration memory solution to configure Virtex-4 FPGAs. Xilinx offers the following options:

• Platform Flash
  
Platform Flash is the simplest and most cost effective configuration memory solution for Virtex-4 FPGAs. Platform Flash is a Xilinx proprietary, single-chip, drop-in solution that is offered in densities ranging from 1-Mb up to 32-Mb.


• Processor Controlled
  Customers who have an onboard processor may opt to use it to configure Virtex-4 FPGAs; a non-volatile memory solution is still required. The following application notes provide details on how to implement a processor controlled configuration solution.
  • XAPP058: Compact JTAG-based configuration method for all Xilinx ISP devices
    
  • XAPP500: IEEE STD 1532 (JTAG-based) configuration method for all 1532-compliant devices
    
  • XAPP502: Compact method for Xilinx slave-serial or slave-SelectMAP configuration modes
    
  • XAPP441: Remote FPGA Reconfiguration Using MicroBlaze™ or PowerPC™
    
    
• Standard Flash Memory
  Some customers may opt to use standard Flash memory to configure Virtex-4 FPGAs. The following application notes explains how to implement.
  
  • XAPP079: Slave-serial configuration from parallel NOR flash
    
  • XAPP137: Slave-SelectMAP configuration from parallel NOR flash

Miscellaneous

• XAPP693: A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs
  


• System ACE CF


• Partial Reconfiguration Application Notes
  • XAPP662: In-Circuit Partial Reconfiguration of RocketIO™ Attributes
    
  • XAPP290: Two flows for Partial Reconfiguration: Module Based or Difference Based
    
  • XAPP660: Dynamic Reconfiguration of RocketIO MGT Attributes


• Virtex-4 Configuration User Guide

Configuration Schemes

Xilinx offers the end user flexibility when configuring a Virtex-4 FPGA. The following schemes are supported by Virtex-4 FPGAs:

Serial

Simplest configuration scheme, serial throughput.

Master Serial

The Xilinx FPGA drives the Xilinx PROM CLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Slave Serial

The Xilinx PROM’s internal oscillator drives the Xilinx FPGA CCLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Slave Serial

An external clock drives the Xilinx PROM CLK and the Xilinx PROM drives the Xilinx FPGA CCLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Slave Serial

An external clock drives both the Xilinx FPGA CLK and the Xilinx PROM CLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Parallel

Parallel configuration for fastest throughput.

Master-SelectMap

The Xilinx FPGA drives the Xilinx PROM CLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

Slave SelectMAP

The Xilinx PROM’s internal oscillator drives the Xilinx FPGA CCLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

Slave-SelectMAP

An external clock drives the Xilinx PROM CLK and the Xilinx PROM drives the Xilinx FPGA CCLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

Slave-SelectMAP

An external clock drives both the Xilinx FPGA CCLK and the Xilinx PROM CLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.