Configuration for Virtex-5 FPGA

Solutions and resources for configuring Virtex-5 FPGAs

Virtex®-5 FPGAs use CMOS Configuration Latches (CCLs) to enable configurable interconnects between routing lines and logic cells. They are volatile devices - they do not retain their configuration when power is removed. To configure a Virtex-5 FPGA, you must reinitialize the CCLs inside the device each time power is cycled. Power up configuration for Virtex-5 FPGAs vary by application.

• Prototyping or Debugging
• In the Field
• Miscellaneous
• Configuration Schemes

Prototyping or Debugging

Customers who are in the prototyping phase have the following options for Virtex-5 FPGA configuration:

• Third Party Cables/Solutions
  Xilinx also works with third party vendors to provide Boundary Scan (JTAG) tools that can be used in prototyping environments, without the need for a non-volatile memory source.

In the Field

In the field, customers must implement a non-volatile configuration memory solution to configure Virtex-5 FPGAs. Xilinx offers the following options:

• Platform Flash XL
  

  The industry's fastest 128 Mb configuration and storage device specially optimized for high-performance Virtex-5 FPGA configuration, flexibility and ease-of-use. This device extends the Xilinx configuration portfolio to 128 Mb and enables a single chip configuration solution for all Xilinx Virtex-5 family devices.

• Platform Flash
  The simplest and most cost effective configuration memory solution for Virtex-5 FPGAs. Platform Flash is a Xilinx proprietary, single-chip, drop-in solution that is offered in densities ranging from 1Mb up to 32Mb.
  
  
• Processor Controlled
  Customers who have an onboard processor may opt to use it to configure Virtex-5 FPGAs; a non-volatile memory solution is still required. The following application notes provide details on how to implement a processor controlled configuration solution.
  • XAPP058: Compact JTAG-based configuration method for all Xilinx ISP devices
  • XAPP500: IEEE STD 1532 (JTAG-based) configuration method for all 1532-compliant devices
    
  • XAPP502: Compact method for Xilinx slave-serial or slave-SelectMAP configuration modes
    
  • XAPP441: Remote FPGA Reconfiguration Using MicroBlaze™ or PowerPC®
    
• Standard Flash Memory
  Xilinx FPGAs are the industry’s first and only FPGAs that provide direct open configuration memory interface. Virtex-5 FPGAs are compatible with most industry standard Flash memories. Xilinx has provided programming of key SPI PROMs starting in iMPACT 8.2i.

Miscellaneous

• UG191: Virtex-5 FPGA Family Configuration User Guide
• XAPP693: A CPLD-Based Configuration and Revision Manager for Xilinx Platform Flash PROMs and FPGAs
  
• System ACE CF
• Partial Reconfiguration Application Notes
  • XAPP662: In-Circuit Partial Reconfiguration of RocketIO™ Attributes
  • XAPP290: Two flows for Partial Reconfiguration: Module Based or Difference Based
  • XAPP660: Dynamic Reconfiguration of RocketIO MGT Attributes
• Virtex-5 FPGA Data Sheet
• Virtex-5 FPGAs
• Platform Flash XL
• Platform Flash

Configuration Schemes

Xilinx offers the end user flexibility when configuring a Virtex-5 FPGA. The following schemes are supported by Virtex-5 FPGAs:

Serial

Simplest configuration scheme, serial throughput.

Master Serial

The Xilinx FPGA drives the Xilinx PROM CLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Slave Serial

The Xilinx PROM’s internal oscillator drives the Xilinx FPGA CCLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Slave Serial

An external clock drives the Xilinx PROM CLK and the Xilinx PROM drives the Xilinx FPGA CCLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Slave Serial

An external clock drives both the Xilinx FPGA CLK and the Xilinx PROM CLK as the Xilinx PROM provides serial (x1) configuration data to the Xilinx FPGA.

Master-SPI

The Virtex-5 FPGA drives the SPI PROM Clock as the SPI PROM provides serial (x1) configuration data to the Virtex-5 FPGA.

 

Parallel

Parallel configuration for fastest throughput.

Master-SelectMap

The Xilinx FPGA drives the Xilinx PROM CLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

Slave SelectMAP

The Xilinx PROM’s internal oscillator drives the Xilinx FPGA CCLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

Slave SelectMAP

An external clock drives the Xilinx PROM CLK and the Xilinx PROM drives the Xilinx FPGA CCLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

Slave-SelectMAP

An external clock drives both the Xilinx FPGA CCLK and the Xilinx PROM CLK as the Xilinx PROM provides byte-wide (x8) configuration data to the Xilinx FPGA.

 

Master-BPI

The Virtex-5 FPGA drives the Parallel Flash PROM as the Parallel Flash PROM provides byte-wide (x8) configuration data to the Virtex-5 FPGA.