Aurora 64B/66B LogiCORE™ IP

Aurora 64B/66B is released as a part of CORE Generator™ software, with a number of configurable parameters. It can be configured by selecting streaming/framing interface, simplex/full duplex data flow, single/multiple MGT’s, reference clock value, line rate, MGT location(s) based on number of MGTs selected, and reference clock source.

The Aurora 64B/66B protocol and its associated designs address the challenge of controlling and managing the MGT’s control interface. With Aurora 64B/66B, one or more MGT’s can be connected to form a communication channel. The Aurora 64B/66B protocol defines the structure of data packets and procedures for flow control, data striping, error handling, and initialization to validate MGT links. Aurora 64B/66B shrink-wraps MGT’s by providing a transparent interface. A simplex Aurora 64B/66B design does not require any sideband signals for its working.

The Aurora 64B/66B Protocol describes the transfer of user data across an Aurora channel. An Aurora 64B/66B channel consists of one or more Aurora lanes. Each Aurora lane is a full-duplex serial data connection. The devices that communicate across the channel are called channel partners. Figure 1-1 illustrates this relationship.

The Aurora Protocol Specification defines the following:

The ABFM 64B/66B models the behavior of the Aurora 64B/66B protocol and can be used to generate stimulus for and to monitor the response of an Aurora 64B/66B interface design, which is referred to as the device under test (DUT). The ABFM 64B/66B provides parameterization of the protocol parameters (for example, the number of lanes) and that can be used to test any implementation of the Aurora 64B/66B protocol with little overhead.

The ABFM 64B/66B provides flexibility, a clean room implementation of Aurora 64B/66B, and improved performance over using another Aurora 64B/66B design to verify the DUT. The ABFM 64B/66B can be easily integrated into an existing verification environment specifically designed to test the DUT.

Once the ABFM 64B/66B is integrated into the verification environment, it can communicate with the DUT using a programming language interface (PLI) for Verilog environments & foreign language Interface (FLI) in case of VHDL for modelsim environment. PLI/FLI contains transaction based calls that are used to establish communication between the DUT and ABFM 64B/66B.

Downloads

• Aurora 64B/66B Protocol Specification & Bus Functional Model The Aurora protocol specification and Bus Functional Model are free and available for download after registration.	Click below for updates.
• Aurora 64B/66B LogiCORE™ IP Generate tailored HDL point solutions for the Virtex™-5 families with the Aurora 64B/66B LogiCORE IP supplied with the Xilinx ISE CORE Generator™. The user-configurable LogiCORE IP is available free of charge through ISE™ after registration and is updated in conjunction with standard Xilinx ISE IP Updates.	Click below for updates.