System Packet Interface (SPI) and SerDes Framer Interface (SFI)

The Optical Internetworking Forum (OIF) System Packet Interface (SPI) and SerDes Framer Interface (SFI) provide the highest performance parallel interfaces commonly used in SONET/SDH and Ethernet applications.

Why use the Xilinx solutions for SPI and SFI?

Our solutions are hardware-proven across multiple FPGA platforms with bandwidth-optimized source code to achieve maximum throughput.

SFI

SFI-S is a SERDES based PHY specification connecting OTN framers and FEC processors to optical modules. SFI-S is a point to point interface which uses CEI SR electricals. The Reference Design uses 10 data channels and one deskew channel, each running at 11.18Gbps to provide a 111.8Gbps total bandwidth solution for Xilinx 7-Series FPGAs.

• See SFI-S Reference Design application note XAPP553
• Download SFI-S Reference Design

SFI-5 reference design supports 40Gbps payload data rates with a generous deskew margin for the receiver to compensate for skew differences.

• See SFI-5 Reference Design application note XAPP882 for Virtex-6
• Download SFI-5 Reference Design for Virtex-6

• See SFI-5 Reference Design application note XAPP871 for Virtex-5
• Download SFI-5 Reference Design for Virtex-5

SFI-4.1 reference design supports up to 710 Mbps/channel with dynamic alignment to provide a robust solution for OC-192 framer interfaces.

• See SFI-4.1 Reference Design application note XAPP856
• Download SFI-4 Reference Design

These reference designs are:

• Fully compliant with the latest Optical Internetworking Forum's (OIF) SerDes Framer Interface SFI- 5 and SFI-4.1 specifications.
• Verified in hardware.

SPI

SPI LogiCORE™ solutions support OC-192 (10 Gbps) and OC-48 (2.5 Gbps) data rates to provide a robust and efficient interface between physical layer (PHY) and link layer devices in a wide range of networking applications and multi-service DWDM- and SONET/SDH-based transport systems. Xilinx SPI cores:

• Fully comply with the latest Optical Internetworking Forum's (OIF) System Packet Interface (SPI) implementation agreements.
• Fully comply with the SATURN® Development Group's POS-PHY interface specifications.
• Enable OC-48/OC-192 POS, ATM, Gb and 10 Gbps Ethernet applications.
• Are verified in hardware to interoperate with link-layer, PHY and NPU devices from companies such as PMC-Sierra, Mindspeed, Vitesse, and Intel®.

Xilinx Solutions by Protocol

Protocol	Market	Applications	Engineer Benefit	FPGA Family
SFI-S	Wired networking	Framer, muxponder, transponder interfaces for OTU4	100 Gb with active deskew channel	7-Series
SFI-5	Wired networking	Framer interfaces for OC-768, 40Gb	40 Gb with generous deskew margin for receiver	Virtex®-6, Virtex-5
SPI-4.2	Wired networking	OC-192, 10 Gb	10 Gb with dynamic alignment	Virtex-6, Virtex-5, Virtex-4
SPI-3	Wired networking	OC-48, 2.5 Gb	Parameterizable 2.5 Gbps	Virtex-6, Virtex-5, Virtex-4, Spartan®-3 Families
SFI-4.1	Wired networking	Framer interfaces for OC-192	Up to 710 Mbps/channel with dynamic alignment	Virtex-5, Virtex-4

Xilinx Solutions for SFI-S by FPGA

FPGA Device	Reference Design Performance	Technical Documents	Verification	Reference Design	Development Board
7-Series	111.8 Gbps payload data rate	Application note XAPP553	Hardware verification on VC7203	Download now (approval required)	VC7203

Xilinx Solutions for SFI-5 by FPGA

FPGA Device	Reference Design Performance	Technical Documents	Verification	Reference Design	Development Board
Virtex-6	40 Gbps payload data rate	Application note XAPP882	Hardware verification on ML623	Download now	ML623
Virtex-5	40 Gbps payload data rate	Application note XAPP871	Hardware verification on ML563	Download now	ML563

Xilinx Solutions for SPI-4.2 by FPGA

FPGA Device	Performance	IP	Technical Documents	Verification	IP Evaluation	Development Board
Virtex-6	10 Gbps	Overview	Data sheet	Hardware interoperability	Evaluate now	Buy now (ML605)
Virtex-5	10 Gbps	Overview	Data sheet	Hardware interoperability	Evaluate now	Buy now (ML550)
Virtex-4	10 Gbps	Overview	Data sheet	Hardware interoperability	Evaluate now	-

Xilinx Solutions for SPI-3 by FPGA

FPGA Device	Performance	IP	Technical Documents	Verification	IP Evaluation
Virtex-6, Virtex-5, Virtex-4, Spartan-3 Families	2.5 Gbps	Link layer	Link layer data sheet	Software verification with Bus Functional Model	Evaluate link layer IP

Xilinx Solutions for SFI-4.1 by FPGA

FPGA Device	Reference Design Performance	Technical Documents	Verification	Reference Design	Development Board
Virtex-5	Up to 710 Mbps/channel with dynamic alignment	Application note XAPP856	Hardware verification on ML550	Download now	Buy now (ML550)