System Packet Interface (SPI) and SerDes Framer Interface (SFI)

The OIF System Packet Interface (SPI) and SerDes Framer Interface (SFI) provide the highest performance parallel interfaces commonly used in SONET/SDH and Ethernet applications.

Why use the Xilinx solutions for SPI and SFI?

Our solutions are hardware-proven across multiple FPGA platforms with bandwidth-optimized source code to achieve maximum throughput.

SFI

SFI-5 reference design supports 40Gbps payload data rates with a generous deskew margin for the receiver to compensate for skew differences.

SFI-4.1 reference design supports up to 710 Mbps/channel with dynamic alignment to provide a robust solution for OC-192 framer interfaces.

These reference designs are:

Fully compliant with the latest Optical Internetworking Forum's (OIF) SerDes Framer Interface SFI- 5 and SFI-4.1 specifications.
Verified in hardware.

SPI

SPI LogiCORE™ solutions support OC-192 (10 Gbps) and OC-48 (2.5 Gbps) data rates to provide a robust and efficient interface between physical layer (PHY) and link layer devices in a wide range of networking applications and multi-service DWDM- and SONET/SDH-based transport systems. Xilinx SPI cores:

Fully comply with the latest Optical Internetworking Forum's (OIF) System Packet Interface (SPI) implementation agreements.
Fully comply with the SATURN® Development Group's POS-PHY interface specifications.
Enable OC-48/OC-192 POS, ATM, Gb and 10 Gbps Ethernet applications.
Are verified in hardware to interoperate with link-layer, PHY and NPU devices from companies such as PMC-Sierra, Mindspeed, Vitesse, and Intel®.

Xilinx Solutions by Protocol
Protocol	Market	Applications	Engineer Benefit	FPGA Family
SFI-5	Wired networking	Framer interfaces for OC-768, 40Gb	40 Gb with generous deskew margin for receiver	Virtex®-5
SPI-4.2	Wired networking	OC-192, 10 Gb	10 Gb with dynamic alignment	Virtex-5, Virtex-4
SPI-3	Wired networking	OC-48, 2.5 Gb	Parameterizable 2.5 Gbps	Virtex-5, Virtex-4, Extended Spartan®-3A Family
SFI-4.1	Wired networking	Framer interfaces for OC-192	Up to 710 Mbps/channel with dynamic alignment	Virtex-5, Virtex-4

Xilinx Solutions for SFI-5 by FPGA
FPGA Device	Reference Design Performance	Technical Documents	Verification	Reference Design	Development Board
Virtex-5	40 Gbps payload data rate	Application note XAPP871	Hardware verification on ML563	Download now	ML563

Xilinx Solutions for SPI-4.2 by FPGA
FPGA Device	Performance	IP	Technical Documents	Verification	IP Evaluation	Development Board
Virtex-5	10 Gbps	Overview	Data sheet	Hardware interoperability	Evaluate now	Buy now (ML550)
Virtex-4	10 Gbps	Overview	Data sheet	Hardware interoperability	Evaluate now	-

Xilinx Solutions for SPI-3 by FPGA
FPGA Device	Performance	IP	Technical Documents	Verification	IP Evaluation
Virtex-5, Virtex-4, Extended Spartan-3A Family	2.5 Gbps	Physical layer Link layer	Physical layer data sheet Link layer data sheet	Software verification with Bus Functional Model	Evaluate physical layer IP Evaluate link layer IP

Xilinx Solutions for SFI-4.1 by FPGA
FPGA Device	Reference Design Performance	Technical Documents	Verification	Reference Design	Development Board
Virtex-5	Up to 710 Mbps/channel with dynamic alignment	Application note XAPP856	Hardware verification on ML550	Download now	Buy now (ML550)