XAUI

• Buy the Virtex™-5 FPGA development board and evaluate reference designs for XAUI solutions.
• Evaluate XAUI LogiCORE™ IP.

The 10 Gigabit Attachment Unit Interface (XAUI), delivers 10 Gbps of data throughput using four differential signal pairs in each direction running at 3.125 Gbps. Its compact nature and robust performance makes it ideal for chip-to-chip, board-to-board, and chip-to-optics module applications.

Why use the Xilinx solution for XAUI?

The Xilinx XAUI core is a fully verified, validated and interoperability tested solution that supports both Verilog and VHDL design flows. In addition, a XAUI protocol characterization report, enables the customer to fine-tune the SERDES parameters unique to the application. See all solutions.

Xilinx Solutions for XAUI: Benefits by Market
Market	Applications	Engineer Benefit	FPGA Family
Wired networking and telecom and wireless	Traffic management, packet classification, backplane interface	Flexible solution for interfacing/ bridging to NPU interfaces	Virtex-5
Aerospace/ defense and industrial	Mezzanine card connectivity	Industrial temperature range	Virtex-5
Storage, audio, visual, broadcast	Blade connectivity using KX4 cables, cabled ethernet backplane	Low power GTPs for power sensitive data center applications	Virtex-5

Xilinx Solutions for XAUI: By FPGA
FPGA Device	IP	Technical Documents	Characterization Report	Boards
Virtex-5 LXT/SXT	Soft IP	Documentation	XAUI technology-specific	Buy now
Virtex-4 FX	Soft IP	Documentation	General	Buy now
Virtex-II Pro	Soft IP	Documentation	General	Buy now

Xilinx Solutions for XGMAC: By FPGA
FPGA Device	IP	Technical Documents	Characterization Report	Boards
Virtex-5 LXT/SXT	Soft IP	Documentation	General	Buy now
Virtex-4 FX/SX/LX	Soft IP	Documentation	General	Buy now
Virtex-II Pro	Soft IP	Documentation	General	Buy now

All solutions are UNH IOL interop tested.

Choose the Correct Solution for Your Application

The 65-nm Virtex-5 SXT/LXT FPGA series is ideal for XAUI applications to meet 10 Gbps data bandwidth needs. It includes:

• Configurable Soft IP solution for XAUI and 10GEMAC.
• Integrated 3.75 Gbps low power RocketIO™ transceivers.
• Example design and demonstration test bench.
• Reference designs.
• Characterization and interoperability reports.

You can design a complete XAUI solution with our simple CORE Generator™ flow.

Delivered through the CORE Generator, XAUI can be configured with the following options:

• Internal XGMII for applications where the core communicates with other logic in the same FPGA.
• External XGMII for when the core is used with logic that is not contained within the same FPGA.
• IEEE 802.3ae-2002 compliant state machines.
• Optional MDIO interface or simplified interface with configuration vector.

The Virtex-4 FX FPGA and Virtex-II Pro FPGAs offer powerful integrated Multi-Gigabit Transceivers (MGTs) and soft IP to enable a solution for XAUI protocol:

• Take our course on RocketIO MGTs.
• Buy the development board to evaluate Virtex-5 LXT FPGA solutions for XAUI.
• Learn more about the soft-IP solution for XAUI protocol in Virtex-5 FPGAs.