Design Entry

The ISE™ Design Suite delivers a complete environment for design capture, including HDL and schematic entry, HDL language templates, state diagrams, IP core placement and reuse, Architecture Wizards for configuring advanced silicon features, floorplanning, advanced design analysis, and systems-level design, while optional productivity tools expand design entry functionality even further.

• Interactive Timing Closure
  Provides a virtual "Timing Closure Cockpit" to help you debug and solve timing issues faster than ever before.

• Project Navigator
  Maximum tool integration and an intuitive graphic interface that drives your project to completion using a design flow-based methodology.

• PlanAhead™ Design Analysis Tools
  Our optional hierarchical floorplanner and design analysis tool that decreases your design time and increases performance by simplifying logic synthesis through physical design.

• System Generator for DSP
  System Generator for DSP is an optional plugin to the MathWorks MATLAB®/Simulink® simulation tool, and provides a high-level design entry and system abstraction that is automatically compiled into a FPGA at the push of a button.

• PACE
  Simplifies complicated pin management and area constraints definitions process.

• CORE Generator™ System
  CORE Generator offers an optimized, predefined set of building blocks and IP for common functions - simplifying design and bringing your project to completion faster.

• Floorplanner
  A graphical placement tool that provides "drag and drop" control over detailed design placement within an FPGA.

• Architecture Wizards*
  Access advanced silicon functionality through a parameterized, GUI-based interface that outputs completely editable HDL code.

• RTL Viewer/Technology Viewer*
  Display pre-synthesis or post-synthesis implementation results in an easy-to-comprehend block-based schematic view.

• Macro Builder*
  Enables design reuse and improves productivity by creating ready-to-use macros with repeatable performance.

• Constraints Editor*
  Simplifies timing-driven design by quickly guiding designers through timing constraint creation without requiring an understanding of complex syntax.

• State Machine Editor*
  Take state machine design from concept through synthesis in minutes.

• Schematic Entry*
  Schematic creation and connection is supported with a complete set of graphic symbol libraries for gate-level and RTL-level design support.

• Language Templates*
  Optimized, ready-to-use Verilog or VHDL language templates for easy insertion into your HDL source files.

• HDL Editor*
  Create and edit Verilog or VHDL source-code using our context sensitive language editor.

* See Documentation for additional information.