Implementation & Configuration

Design implementation is the process of translating, mapping, placing, routing and generating a bitstream file for your design. With Xilinx Fmax Technology, ISE™ software provides the solution for optimal design performance in the least amount of time.

• SmartCompile™ Technology
  SmartCompile Technology offers a suite of tools to help FPGA designers realize dramatically faster runtimes by preserving synthesis, placement, and routing information.
• SmartXplorer
  SmartXplorer allows users to achieve maximum performance through distributed processing.
• Device Programming
  All ISE configurations include iMPACT, allowing users to easily perform device configuration and programming either as a batch operation or through a convenient graphical user interface.
• Timing-Driven Place and Route
  Xilinx invented Timing-Driven Place and Route for programmable logic. In ISE when you specify timing requirements for critical paths, performance is dramatically improved through tools such as Timing Analyzer, Constraints Editor with Time Specs, FPGA Editor, and Floorplanner.
• PlanAhead™ Lite
  PlanAhead Lite, a subset of the award winning PlanAhead Design and Analysis Tool, includes ExploreAhead to help simplify implementation by managing multiple implementation processes.

• PlanAhead Design Analysis Tools
  Our optional hierarchical floorplanner and design analysis tool that decreases your design time and increases performance by simplifying logic synthesis through physical design.

• Translate and Map*
  ISE performs all the steps necessary to read a netlist file in EDIF format and it creates an output file describing the logical design (a logical design is in terms of logic elements such as AND gates, OR gates, decoders, flip-flops, and RAMs).

• Timing-Driven Map*
  The ISE timing-driven map technology helps you lower device cost. With an exclusive timing-driven map option, you can achieve better design utilization for your FPGA device, particularly if the device is already more than 90% utilized. Timing-driven map is a next-generation enhancement to ISE physical synthesis, and combines placement with logic slice packing to improve placement quality for “unrelated logic.”

• Device Configuration*
  Configuring the programmable logic device is the last step in your design methodology. A bitstream is generated from the physical place and route information and is transferred through cables to the target device.

• Push-Button Design Flows*
  The ISE Project Navigator guides you through a simple push-button flow to implement designs automatically. For more complex designs, you have complete control over every aspect of the design flow process.

* See Documentation for additional information.