| The Xilinx FPGA architecture is designed with efficient configurable logic blocks (CLBs) and high-speed multipliers, block RAMs, distributed RAM, and memory interfaces that drastically reduce logic delay. This process technology uses smaller geometries than previous FPGA generations. As a result, gate delays and system clock frequencies are greatly improved.
However, basic Hardware Description Language (HDL) code often does not guarantee the desired clock frequency, and fine-tuning might be necessary. To facilitate high-speed system design, Xilinx software comes with an array of tools and options. Below are some recommended high-speed system design tools: |
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Analog Simulation Tools
Analog simulation is a necessary part of PCB and system design. Xilinx has chosen to support simulation of our products through IBIS I/O models. Here's where you can find the models and simulators to use them in. |
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HDL Techniques
Although synthesis tools allocate FPGA hardware resources quite well, they cannot match the ability of the designer to make additional timing improvements by using several HDL coding tricks. Some of these tricks include using good language constructs, designing a circuit in parallel fashion instead of in serial, using efficient pipelining, and partitioning hierarchical modules. These
techniques can avoid the large delays that might arise from long combinatorial delays. Designers can use architecture-specific primitives and macros, such as embedded multipliers, to improve performance. |
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Timing Analyzer
The Timing Analyzer software allows hardware designers to see timing bottlenecks in a design that might prevent it from meeting a target clock frequency. Detailed paths can be viewed, not only in tabular format but actually in the Floorplanner tool, using the new cross-probing function. By showing detailed critical paths, this software helps designers identify blocks of HDL code that
need to be improved. The identified blocks can be constrained in the Place-and-Route software to improve performance. The new Timing Improvement Wizard tool available in the software gives step-by-step advice on how to improve timing. |
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Constraints Editor
One of the simplest ways to achieve better performance is to place constraints on a design. Constraints can be entered either in the HDL code or, as an option, in the Place-and-Route software. Many different constraints can be used. Below is a list in order of complexity:
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Floorplanner
The floorplanning tool provides a way for designers to visualize how resources are allocated and placed within a device. This tool also enables designers to manually place their design blocks at any desired locations within the device, instead of writing location constraints in a file. Correct and careful placement of design blocks, keeping data flow in mind, often leads to better
timing. |
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