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Sixteen low-skew global clock lines and up to twelve Digital Clock Manager (DCM) circuits provide superior flexibility for high-performance clocking. The feedback in each DCM can be used to eliminate on-chip clock delay or even board clock delay. Each DCM has nine clock outputs and can drive up to four global clocks. The clock outputs provide coarse phase shifting with four-quadrant
outputs. The clock can also be phase shifted during configuration or phase stepped during operation, all with a resolution of 256 steps per clock period. Multiples and fractions of the clock frequency are available. The FX output even provides simultaneous multiplication and division of the input frequency by any set of numbers up to 32.
Since the DCM can eliminate the clock distribution delay, all flip-flops (even in the largest device) are clocked with a timing skew of less than 100ps. This eliminates concerns about internal hold time issues and guarantees short pin-to-pin input setup times as well as short clock-to-output delays.
For systems with a common (system-synchronous) clock distribution on the PCB, there is never an input hold time requirement, and outputs have a specified (min) delay. I/O performance is determined by the max pin-to-pin parameters and is almost independent of chip size. Source-synchronous systems using clock forwarding have a narrow data capture window, in which the clock can
be phase adjusted to capture data in the middle of the arriving eye pattern.
In the system-synchronous timing diagram without DCM, the internal clock signal is delayed by the clock distribution within the chip. This increases the output delay and makes the input set-up time less predictable. Since the DCM can eliminate the on-chip clock distribution delay, it increases the total timing margin.
The receiver must recover the data by clocking it at the right time, close to the center of the valid data eye pattern. The diagram below shows how skew, jitter, and duty cycle distortion reduce the width of the data valid windows.
The above diagram shows that the effective data sampling window is reduced due to various distortions. Virtex-II devices are designed to maximize the sampling window, preventing timing issues due to small sampling windows.
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Clock Data Recovery (CDR) Resources