Xilinx : Clock Data Recovery (CDR)

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Clock Data Recovery (CDR)

Clock Data Recovery (CDR) technology is a key capability in high-performance systems. In addition to fast logic in the FPGA, high-performance systems require reliable, high-speed data transmission between devices. Having a high bandwidth transmitter/receiver link does not necessarily guarantee access to such bandwidth -- the ability to recover data from the distortion and noise in a transmission channel determines the real available reliable bandwidth of a network. Data recovery is a fundamental block for long-haul and dense-wavelength division multiplexing (DWDM) optical networks, as well as for high-speed inter-chip and backplane connections, and fiber-channel, wireless, and storage area networks.

Application Notes	To view PDF files below
Data Recovery Solutions

Clock Data Recovery (CDR) Resources
Application Notes
XAPP224 - Data Recovery This application note and reference design outline a method to implement clock and data recovery in Virtex-II™ devices. Although not limiting the implementation to a specific FPGA family, this reference design focuses on the Virtex-II architecture. With minor modifications, Clock and Data Recovery (CDR) is possible with Virtex-E™ and Spartan-IIE™ devices. A implementation of CDR at 270 Mbps with 8B/10B coded data is described herein. XAPP250 - Clock and Data Recovery With Coded Data Streams This application note and reference design outline a method to implement clock and data recovery in Virtex-II™ devices. Although not limiting the implementation to a specific FPGA family, this reference design focuses on the Virtex-II architecture. With minor modifications, Clock and Data Recovery (CDR) is possible with Virtex-E™ and Spartan-IIE™ devices. A implementation of CDR at 270 Mbps with 8B/10B coded data is described herein. Note: Designs not requiring a recovered clock should refer to a specific Data Recovery application note, XAPP224.
Data Recovery Solutions
A 210 Mbps CDR Solution for Virtex-II™ FPGAs This solution uses a receiver clock that is slightly faster than the transmitter clock. The received data stream's edges are used for data retiming. This is ideal for systems where the data and clock are both transmitted to the receiver, or when the date frequency is known. Data retiming is the focus of this solution. For more information see application note XAPP224 information listed above. Clock Deskewing Clock Deskewing. A common problem in storage area networks and backplanes is clock corruption. If the clock and data are not embedded together, the clock goes out of phase at the receiver end due to skew. At high frequencies, signal propagation delay and reflections that occur in conductors that are only a few centimeters long must be taken into account. SelectLink Verilog Source Code Generator For Virtex™/Virtex-E FPGAs The SelectLink tool allows logic designers everywhere to instantly create customized SelectLink Verilog source code. The modules are easily instantiated in the designers top level code for a complete system solution.

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