Xilinx : High-Performance Low Voltage Differential Signal (LVDS)

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High-Performance Low Voltage Differential Signal (LVDS)

As the need for higher bandwidth accelerates, system designers are choosing differential signalling to satisfy high bandwidth requirements while reducing power. To ensure data integrity across PCB layout, Xilinx Virtex™-II and Virtex-E I/O pin architectures support LVDS standards. It has been shown that LVDS is able to keep data stable across long PCB traces at 840 Mbps on a Virtex-II device. LVDS is ideal for ensuring strong and stable clock signals in source-synchronous clock designs. This feature can be turned on or off by instantiating the LVDS standard in a the HDL code.

Xilinx provides several application notes and reference designs that showcase Virtex-II and Virtex-E LVDS performance. These include the following:

Application Notes	To view PDF files below

High-Performance Low Voltage Differential Signal Resources
Application Notes
XAPP265: Virtex-II 840 Mbps LVDS Design Data serialization and deserialization (SerDes) is often a requirement in digital system design. Serialized data reduces the number of pins needed for a design. The Virtex-II™ LVDS reference design provides 8:1 and 7:1 SerDes implementations. Both implementations support transfer in either 4 or 16 data channels. This reference design is capable of LVDS performance at 840 Mbps per channel, and thus an aggregate data transfer of over 13 Gbps.
XAPP245: Eight-channel, one-clock, one-frame LVDS transmitter/receiver (Virtex-E Devices) This reference design provides a 5.12 Gbps transmitter and receiver interface using ten Virtex-E™ LVDS pairs (eight data channels, one clock, and one frame). A library of LVDS designs is provided from which designers can pick the ideal device-package combination for their specific system design. The LVDS design is implemented as a EDIF netlist with embedded location constraints and VHDL and Verilog simulation files. The LVDS design does not rely on guide files for successful performance.
XAPP243: Bus LVDS with Virtex-E Devices This application note describes how to use the Virtex-E™ Bus Low Voltage Differential Signaling (BLVDS) technology in high-performance multipoint applications. BLVDS extends the benefits of standard LVDS into multipoint configuration, supporting bidirectional backplanes. Spice simulation results show that this design can operate up to 200 MHz.
XAPP233: Multi-Channel 622 Mbps LVDS Data Transfer for Virtex-E Devices The reference design for the LVDS 622 Mbps receiver uses two data channels and one clock channel. The system relies on double-data-rate (DDR) clocking.
SelectLink SelectLink technology communications channels use standard features of the advanced Xilinx FPGA families such as delay lock loops (DLLs), block RAM, and programmable SelectIO™ and SelectIO+ technologies. SelectLink technology can be used to create a system that delivers throughput of more than 311 Megabits per second (Mbps) per pin for bus widths up to 256 pins.The web-based SelectLink tool allows logic designers anywhere to instantly create customized Verilog source code using their specific internal and external data buses and FPGA resources. The tool generates in seconds Verilog code and test benches that easily can be integrated into the rest of the system design. This code generator support LVDS for Virtex and Virtex-E.

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