Memory Solutions

Buy Spartan-3A FPGA Development Kit for DDR2 SDRAM

Xilinx memory interface solutions are based on hardware-verified reference designs and software tools that enable you to quickly generate your own custom design.

View Video: Memory Interface Design with MIG 2.0

Simplify memory device selection and controller implementation with the following application notes, reference designs and the Memory Interface Generator (MIG).

Memory Interface Support for FPGAs
Memory Type	Virtex™-5	Virtex-4	Spartan™-3 Generation
DDR3 SDRAM	800 Mbps 400 MHz	-	-
DDR2 SDRAM	667 Mbps 333 MHz	600 Mbps 300 MHz	400 Mbps* 200 MHz
DDR SDRAM	400 Mbps 200 MHz	344 Mbps 172 MHz	333 Mbps 166 MHz
QDR II SRAM	2 x 600 Mbps 300 MHz	2 x 550 Mbps 275 MHz	-
RLDRAM II	667Mbps 333 MHz	470 Mbps 235 MHz	-

*Spartan-3A/AN devices support 400 Mbps DDR2 interfaces (see Application Note: XAPP458)

Additional Memory Resources by FPGA

Virtex-5 FPGAs

White paper: Memory Interfaces with Xilinx FPGAs (PDF)
Development platform: ML561
Characterization test report: DDR2 controller interface

Virtex-4 FPGAs

Development platform: ML461

Spartan-3 Generation FPGAs

DDR2 reference design and DDR2-400 video demo for the Spartan-3A Starter Kit board and DDR2 Development Kit. Registered users may download complete files.
First time users | Registered users

Spartan-3A DDR2 SDRAM Interface Development Kit

DDR reference design for the Spartan-3E Starter Kit. Registered users may download complete files.
First time users | Registered users

Memory Interface Generator (MIG)

Generate your Virtex-5, Virtex-4, and Spartan-3 generation memory interface reference designs, including HDL code and pin placements, using this user-friendly tool.

First time users | Registered users

Registered users may download the User Guide and the MIG tool. The User Guide contains information such as recommended pin constraints, PCB trace matching, termination schemes, clock-capable IO rules, bank recommendations, DCI, and ODT suggestions.

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