DDR2 Controller Interface for Virtex-5 FPGA - Characterization Report

This DDR2 controller interface characterization test report contains a set of data taken on the ML561 board over process, voltage and temperature (PVT) variations. In all tested cases, the DDR2 interface reference design performance exceeded maximum specifications and provided ample design margins for high performance applications.

The DDR2 reference design, like all other Xilinx memory interface reference designs, is fully hardware verified. While included with the Memory Interface Generator (MIG), it can also be downloaded separately.

The DDR2 controller and interface implemented using Virtex®-5 FPGA was extensively tested under these conditions:

• Slow process corner for each speed grade
• Voltage variations +/- 3%
• Temp. variations 0-85 C
• Data patterns: PRBS and Hammer

ML561 board and test equipment used for PVT characterization.

 

Screenshot of junction temperature ramp with System Monitor.

DDR2 DIMM write hardware measurement (DQ) – 333MHz, low voltage, 85 ºC.

To get the full characterization test report or arrange a demo, please contact your sales representative.