DDR3 SDRAM

An Evolutionary Step Forward

DDR3 SDRAM architecture extends the capabilites of DDR2 SDRAM, providing:

• Lower power consumption (1.5V vs. 1.8V I/O and power supply).
• Improved I/O signaling for better signal integrity.
• Increased data rates for higher system performance.

Our free DDR3 memory controller reference design leverages Virtex™-5 FPGA features such as IODELAY, a programmable input and output delay block that ensures accuracy of read data capture and configurable write data signals to meet 800 Mbps data rates and DDR3 SDRAM functional requirements. 

Xilinx is currently shipping the ML561 hardware evaluation platform that supports DDR3 SDRAM devices with dual x16 bit wide available footprints.

ML561 evaluation platform with two (x16) 800 Mbps DDR3 SDRAM devices.

Successful interoperability compliance hardware tests were performed using 800 Mbps DDR3 SDRAM devices from leading memory manufacturers.

Signal eye diagram captured at the DDR3 SDRAM device inputs during 800 Mbps (400 MHz) operation.

Application Notes and Reference Designs for Virtex-5 FPGAs

XAPP867- Implementing DDR3 Interfaces in Virtex-5 FPGAs
DDR3 Reference design: First time users, Registered users

XAPP867 describes the DDR3 SDRAM reference design including the controller and the capture technique for high performance 800 Mbps interfaces.

Memory Vendors