DDR/ LPDDR/ DDR2 SDRAM

New features and functions enable higher clock and data rate operations. Built-in capabilities of Virtex®-6 FPGAs and Spartan®-6 FPGAs enable DDR2 SDRAM interfacing at data rates of 800 Mbps.

Application Notes and Reference Designs

Virtex-6 FPGAs (DDR2)

UG406 - Virtex-6 FPGA Memory Interface Solutions User Guide
The Virtex-6 FPGA Memory Interface Solutions User Guide provides information about using, customizing, and simulating LogiCORE™  IP memory interface cores for the Virtex-6 FPGA.

Spartan-6 FPGAs (DDR2, DDR, LPDDR)

UG388 - Spartan-6 FPGA Memory Controller User Guide

UG416 - Spartan-6 FPGA Memory Interface Solutions User Guide

Virtex-5 FPGAs (DDR2, DDR)

XAPP858 - High-Performance DDR2 SDRAM Interface Data Capture with Virtex-5 FPGAs (PDF)

XAPP851 - DDR SDRAM Controller Using Virtex-5 Devices (PDF)

Extended Spartan-3A Family (DDR2, DDR)

XAPP458 - Implementing DDR2-400 Memory Interfaces in Spartan-3A FPGAs (PDF)

XAPP454 - Spartan-3 FPGA DDR2 Memory interface (PDF)
HDL Code: First time users | Registered users

XAPP768c - 166 MHz DDR Interface For Spartan-3 HDL Code (PDF, login required)
HDL Code: First time users | Registered users

Virtex-4 FPGAs (DDR2, DDR)

XAPP721 - High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES (PDF)

XAPP723 - DDR2 Controller  for ISERDES and OSERDES Interface Using Virtex-4 Devices (PDF)

XAPP701 - Memory Interfaces Data Capture Using Direct Clocking Technique (PDF)

XAPP702 - DDR-2 Controller Using Virtex-4 Devices (PDF)

XAPP709 - DDR SDRAM Controller Using Virtex-4 Devices (PDF)

Other Resources

Online Demo: Memory Interface Design with MIG 3.3

Memory Vendors

 Micron Technology DDR2 SDRAM Data Sheets