DDR/DDR2 SDRAM

Go beyond DDR (Double Data Rate)

New features and functions enable higher clock and data rate operations. Built-in capabilities of Virtex™-5 FPGAs enable DDR2 SDRAM interfacing at data rates of 667 Mbps.

White Papers

WP260 - Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface Generator (PDF)

Application Notes and Reference Designs

Virtex-5 FPGAs

XAPP858 - High-Performance DDR2 SDRAM Interface Data Capture with Virtex-5 FPGAs (PDF)

XAPP851 - DDR SDRAM Controller Using Virtex-5 Devices (PDF)

Spartan™-3 Generation FPGAs

XAPP458 - Implementing DDR2-400 Memory Interfaces in Spartan-3A FPGAs (PDF)

XAPP454 - Spartan-3 FPGA DDR2 Memory interface (PDF)
HDL Code: First time users | Registered users

XAPP768c - 166 MHz DDR Interface For Spartan-3 HDL Code (PDF, login required)
HDL Code: First time users | Registered users

Virtex-4 FPGAs

XAPP721 - High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES (PDF)

XAPP723 - DDR2 Controller  for ISERDES and OSERDES Interface Using Virtex-4 Devices (PDF)

XAPP701 - Memory Interfaces Data Capture Using Direct Clocking Technique (PDF)

XAPP702 - DDR-2 Controller Using Virtex-4 Devices (PDF)

XAPP709 - DDR SDRAM Controller Using Virtex-4 Devices (PDF)

Other Resources

Memory Interface Generator (MIG)

Generate your Virtex-5, Virtex-4, and Spartan™-3 generation memory interface reference designs, including HDL code and pin placements, using this user-friendly tool.

 First time users | Registered users

Online Demo: Memory Interface Design with MIG 2.0

Memory Vendors

 Micron Technology DDR2 SDRAM Data Sheets

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