PACE (Pinout and Area Constraint Editor)

PACE helps simplify the ever more complicated pin management and area constraints definitions process.

ISE™ software includes PACE (Pinout and Area Constraints Editor), a powerful, yet fast and easy way to map design pins to your device, and floorplan logic areas. Drag-and-drop pins onto a graphical display of the device, group pins logically by color-coding for easy recognition, specify I/O standards and banks, assign and place differential I/Os, and much more. As devices grow ever larger, PACE brings a new level of ease to the difficult task of assigning design pins.

PACE allows area mapping by examining the defined HDL hierarchy and checks logic areas against expected gate size, making area definitions quick, accurate, and easy. Pins can be assigned using PACE before HDL coding has even started, and then write the HDL starting templates for you to edit. Pin information can be exported or imported to PCB layout editors through standard CSV files, greatly simplifying the design planning stage.

Key Features

• View and edit location constraints for I/Os and global logic
• Create area constraints for hierarchical symbols in your design
• Assign connectivity and resource requirements of your design
• Determine resource layout of your target FPGA
• See how your design maps onto the FPGA via location and area constraints
• Design rule checks to help identify potential problems

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