SmartCompile Technology

ISE™ SmartCompile™ Technology help designers with their #1 problem – timing closure

SmartCompile Technology helps FPGA designers realize dramatically faster runtimes. SmartCompile is comprised of three new features; SmartGuide™, Partitions, and SmartPreview™ technologies .

SmartGuide minimizes implementation differences between two versions of the same design. SmartGuide can be enabled with minimal changes to an existing design flow. Faster runtimes will be realized and timing will be preserved for small design changes that are not on a critical path.

Partitions deliver guaranteed preservation of existing implementation. Users can define Partitions, or hierarchical blocks, within their design. They can then specify that the synthesis, placement, and/or routing of these partitions are to be preserved during re-implementation.

SmartPreview allows users to pause and resume implementation. This allows user to save intermediate results, view state of design (paths that fail timing, routing status), generate bitstreams, and perform timing analysis. This reduces the impact of long implementation cycles by providing insight into the implementation process.