Physical Synthesis

Physical Synthesis solves timing closure problem.

Physical synthesis refers to the ability of creating a properly placed and routable circuit from the HDL code that meets the realistic performance goals of the design in one pass. In the traditional programmable logic design flow, logical synthesis and physical implementation are two separate design stages. This often causes the timing closure problem when designs cannot meet their realistic timing objectives. Merging logical synthesis and physical implementation technologies creates properly placed and routable designs that meet realistic performance goals.

The unique physical synthesis capabilities of ISE are jointly developed with leading third party synthesis vendors. This seamless integration between the physical timing information and the multiple physical synthesis engines delivers optimized results.