H.264 Baseline Encoder w/AXI support - Micro Footprint Core
Part Number:
H264B-AXI - Micro Footprint
AXI Interface Support:
- AXI4
- AXI4-Lite
Alliance Program Tier:
Certified
Design Tools Support:
- ISE Design Suite
- Vivado Design Suite
Device Family Support
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6
- Spartan-6
A2e's H.264-15 core represents a huge leap in performance with just a small increase in size over our previous generation core and is still 80% smaller than other solutions. Encoding performance has been doubled with just a 25% increase in gate count. A single H.264-15 core is capable of compressing 1080p30 video in a Spartan 6 device. Additionally, we’ve added a more flexible bus interface that allows simultaneous and asynchronous access to reference frame memory, video input data, and compressed data (in or out). Support for the latest Xilinx devices such as Zynq and Kintex and AXI bus has also been added. A complete IP camera can now be created in a single, low-cost Zynq device!
Key Features
- Fully compatible with the ITU-T H.264 specification
- Profile level 3.1 is supported
- Generates I and P frames
- Entropy Encoding: CAVLC
- Supports YUV 4:2:0 video input
- Highly optimized Xilinx FPGA Footprint
- Variable Bit Rate (VBR) and Constant Bit Rate (CBR)
- Fully synchronous design
- Search range: 80 x 48 pixels, Full, ½, ¼ pixel resolution
- Support for Single or Multiple slices via firmware control
- Support for intra 4 x 4 DC prediction
- Supports resolutions up to 4096 x 4096 (multiple instantiations)
- Supports simultaneous encoding of multiple streams of arbitrary sizes and compression ratios
- Pre-packaged for Coregen via IP-XACT
- Verilog Source and Netlist versions available
Target Markets
- Aerospace & Defense
- Broadcast
- Consumer
- Industrial Scientific Medical
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-7000 Family | XC7Z020 | -1 | ISE 14.3 | Y | 3939 | 9825 | 9 | 8 | 0 | 0 | 131 |
| Spartan 6 Family | XC6SLX150 | -3 | ISE 14.3 | Y | 3945 | 10505 | 22 | 8 | 0 | 0 | 87 |
| VIRTEX6LXT Family | XC6VLX130T | -2 | ISE 14.3 | Y | 3936 | 9804 | 9 | 8 | 0 | 0 | 142 |
| Kintex-7 Family | XC7K160T | -3 | ISE 14.3 | N | 3939 | 10226 | 9 | 8 | 0 | 0 | 200 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | Feb 26,2013 |
| Company Name | A2E Technologies, LLC |
| IP Name | H.264 Baseline Encoder w/AXI support - Micro Footprint Core |
| IP Part Number | H264B-AXI - Micro Footprint |
| Current IP Revision Number | V2.00 |
| Date Current Revision was Released | Jan 31,2012 |
| Release Date of first Version | Aug 23,2011 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 4 |
| Can references be made available? | N |
| Deliverables | |
| IP Formats available for purchase | Netlist; Source Code |
| Source Code Formats(s) | Verilog |
| High-Level Model Included? | Y |
| High-level Model Format(s) | C |
| Integration Testbench Provided | Y |
| Integration Techbench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | Y |
| FPGA used on board | Other |
| Software Drivers Provided? | Y |
| Driver OS Support | NA |
| Implementation | |
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported / version | Xilinx XST / 12.3 |
| Static Timing Analysis Performed? | Y |
| Standard IP Interface(s) Supported | AXI-4; AXI-Lite |
| IP-XACT Metadata Included? | Y |
| Verfification | |
| Is a documented verification plan available? | Executable and documented plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators supported | Mentor ModelSIM / 6.5d |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | Xilinx ZC-702 with Avnet FMC |
| Industry standard compliance testing passed | N |
| Specific compliance test | NA |
| Are test results available? | N |
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