logiSDHC
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The logiSDHC is the Secure Digital (SD) card Host Controller IP core from the Xylon logicBRICKS IP core library. It is designed to transfer data from the system memory to the SD card's data bus, and vice versa. Implemented DMA mechanism enables a fast data transfer requiring minimal CPU activities.
The logiSDHC IP core is SD Host Controller Standard Specification Version 2.00 compliant. The IP supports non-DMA, standard DMA and Xylon's proprietary DMA transfers, and enables expansion of embedded systems based on the Xilinx FPGA devices by mass storage capabilities.
The logiSDHC supports ARM AMBA AXI4 bus and can be implemented in the latest Xilinx 7 series FPGAs, like the Kintex(TM)-7 FPGA. The logiSDHC is, like the other IP cores from the Xylon logicBRICKS IP library, fully embedded into Xilinx Platform Studio (XPS) and the EDK integrated software solution.
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| KINTEX-7 Family | XC7K325T | -2 | Vivado 2012.1 | Y | 732 | 1553 | 2 | 1 | 0 | 0 | 270 |
| Spartan 6T Family | XC6SLX45T | -2 | 14.1 | Y | 787 | 1670 | 2 | 1 | 0 | 0 | 170 |
| VIRTEX6LXT Family | XC6VLX240T | -3 | 14.1 | Y | 766 | 1583 | 2 | 1 | 0 | 0 | 320 |
| General Information | |
| This Data was Current On | May 24,2012 |
| Company Name | Xylon d.o.o. |
| IP Name | logiSDHC SD Card Host Controller |
| IP Part Number | logiSDHC |
| Current IP Revision Number | 1.5 |
| Date Current Revision was Released | Sep 29,2011 |
| Release Date of first Version | Mar 05,2009 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 5 |
| Can references be made available? | N |
| Deliverables | |
| IP Formats available for purchase | Netlist; Source Code; Bitstream |
| Source Code Formats(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Techbench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | Y |
| FPGA used on board | Spartan-6 |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux |
| Implementation | |
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Instantiation; Inference |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported / version | Xilinx XST |
| Static Timing Analysis Performed? | N |
| Standard IP Interface(s) Supported | AXI-Lite; AXI-4 |
| IP-XACT Metadata Included? | N |
| Verfification | |
| Is a documented verification plan available? | No |
| Test Methodology | Both |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators supported | Mentor ModelSIM |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | logiTAP Platform for Embedded GUI System Developments |
| Industry standard compliance testing passed | N |
| Are test results available? | N |
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