Bit Block Transfer 2D Graphics Accelerator
Part Number:
logiBITBLT
AXI Interface Support:
- AXI4
License:
SignOnce
Alliance Program Tier:
Premier
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
Device Family Support
- Virtex-4 SX
- Virtex-II Pro
- Virtex-II
- Spartan-6 LX
- Virtex-4 LX
- Spartan-6 LXT
- Spartan-6 XA
- Spartan-3A
- Spartan-3AN
- Spartan-3E
- Spartan-3 XA
- Spartan-3
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6 -1L
- Virtex-6 HXT
- Virtex-6 CXT
- Virtex-6 LXT
- Virtex-6 SXT
- Virtex-5 FXT
- Virtex-5 LX
- Virtex-5 LXT
- Virtex-5 SXT
- Virtex-5 TXT
- Virtex-4 FX
This 2D graphics accelerator transfers graphics objects from one to another part of system's on-screen or off-screen video memory. The core also performs different operations during transfers, such as ROP2, Color Expansion, Transparency, and Porter & Duff compositing rules. The IP can be efficiently used for most common Graphical User Interface (GUI) operations. The logiBITBLT is fully embedded into Xilinx Platform Studio and EDK tools, and its integration with on-chip buses is very simple. Parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface. The logiBITBLT can be smoothly integrated with other logicBRICKS IP cores for building of high-class embedded graphics solutions. Xylon provides extensive software support (drivers) for popular OSes like Linux and Windows CE.
Key Features
- Anti-aliased 8-bit font expansion
- Color expansion for font acceleration
- Color keyed transparency
- Controllable Pixel Alpha blending factors
- Pattern BITBLT
- Porter & Duff digital image compositing rules
- RLE (Run Length Encoding) decompression
- RLE decompression
- Solid fill with any color
- Supported image formats: RGB8, ARGB8, RGB16, ARGB16, RGB24 and ARGB24
- Supports 16 different ROP2 binary raster operations
- Supports positive and negative MOVE operations without picture artifacts caused by picture overlapping
Target Markets
- Aerospace & Defense
- Automotive
- Broadcast
- Consumer
- High Performance Computing
- Industrial Scientific Medical
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX5LX Family | XC5VLX30 | -3 | 14.1 | Y | 612 | 1287 | 4 | 0 | 0 | 0 | 234 |
| Spartan 6 Family | XC6SLX45 | -3 | 14.1 | Y | 472 | 1458 | 4 | 0 | 0 | 0 | 130 |
| SPARTAN3E Family | XC3S1600E | -5 | 14.1 | Y | 1257 | 1852 | 4 | 0 | 0 | 0 | 120 |
| VIRTEX6LXT Family | XC6VLX75T | -3 | 14.1 | Y | 467 | 1456 | 4 | 0 | 0 | 0 | 260 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | May 24,2012 |
| Company Name | Xylon d.o.o. |
| IP Name | Bit Block Transfer 2D Graphics Accelerator |
| IP Part Number | logiBITBLT |
| Current IP Revision Number | 2.0 |
| Date Current Revision was Released | Dec 14,2010 |
| Release Date of first Version | Mar 19,2009 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 16 |
| Can references be made available? | N |
| Deliverables | |
| IP Formats available for purchase | Bitstream; Netlist; Source Code |
| Source Code Formats(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Techbench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | Y |
| FPGA used on board | Spartan-6 |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux, WEC7 |
| Implementation | |
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference; Instantiation |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported / version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| Standard IP Interface(s) Supported | AXI-4; AXI-Lite |
| IP-XACT Metadata Included? | N |
| Verfification | |
| Is a documented verification plan available? | Yes, document only plan |
| Test Methodology | Constrained random testing |
| Assertions | Y |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators supported | Mentor ModelSIM |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | logiTAP |
| Industry standard compliance testing passed | N |
| Are test results available? | N |
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