PreciseTimeBasic IEEE 1588 V2 IP Core
- Part Number: S-3101
- Vendor: SOC-E
- Partner Tier: Elite Certified
Product Description
PreciseTimeBasic is a IEEE1588-2008 V2 compliant clock synchronization IP core for AMD FPGAs. It is capable of accurately time stamp IEEE 1588 telegrams and also to provide a compatible time.
PreciseTimeBasic IP comprises different hardware and software elements - A hardware Time Stamping Unit (TSU) capable of accurately time stamp IEEE 1588 event messages and to provide an adjustable timer with submicrosecond precision. Two versions of TSU are provided with the PreciseTimeBasic: PTB TSU and PTBLite TSU.
PTB TSU has been designed to be connected to the Medium Independent Interface ([G]MII), between MAC and PHY, parsing all the Ethernet frames and inspecting which ones are IEEE 1588. PTBLite TSU takes advantage of the PTP parser contained in the Zynq GMACs to provide a TSU usingless FPGA resources but with some limitations imposed by the IEEE 1588 hardwired logic on the PS GMAC.
With the IP, a software PTP Reference Design is also included. Additionaly, SoC-e provides a Linux kernel patch that allow accessing the TSUs using the Linux PTP Hardware Clock (PHC) subsystem.
Key Features and Benefits
- IEEE 1588-2008 clock synchronization system
- Available for Vivado and XPS
- 100/1000 Mbps Ethernet
- PPS output
- IRIG-B Master output
- Compatible with different PTP SW stacks
- OC and CB working modes
- E2E and P2P delay mechanism
- Supports PTP on Layer 2 (Ethernet) and Layer 3 (IPv4)
- Support VLAN tagged PTP messages
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU3CG | -1 | Vivado 2020.1 | Y | 397 | 2300 | 5 | 0 | 0 | 0 | 125 |
| Zynq-7000 Family | XC7Z020 | -1 | Vivado 2020.1 | Y | 397 | 2300 | 6 | 0 | 0 | 0 | 125 |
IP Quality Metrics
General Information
| This Data was Current On | Mar 12, 2024 |
| Current IP Revision Number | 19.06 |
| Date Current Revision was Released | Jun 30, 2019 |
| Release Date of First Version | Dec 12, 2011 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 20 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Bitstream, Netlist, Source Code |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq-7000 |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | No |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim / 2018.3 |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | SMARTzynq |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | ISPCS2011,12,13,14,15 |
| Test Date | Dec 10, 2020 |
| Are Test Results Available? | N |