Analyze RTL™
Part Number:
Analyze RTL
Alliance Program Tier:
Member
Design Tools Support:
- ISE Design Suite
- Vivado Design Suite
Device Family Support
- Zynq-7000
- Artix-7
- Kintex-7
- Virtex-7
- Virtex-6
- Virtex-6 LX
- Virtex-5
- Virtex-4
- Spartan-6
Blue Pearl’s Analyze RTL™ combines the ease-of-use methodology and extensive analysis of super-lint tools with the power of formal verification into a single high performance, high capacity design checking solution. With Blue Pearl, you get a unique combination of powerful built-in checks and formal analysis that gives you the most comprehensive and powerful static design checking capability available. Deploy Blue Pearl early and eliminate complex design errors at all stages of your design implementation cycle and drastically reduce the amount of effort you spend finding bugs later using time-consuming traditional test-bench methods.
Key Features
- Automatically extract design properties
- Detect clock domain synchronization errors
- Detect races before simulation
- Find design for testability errors at RTL stage
- Visual Verification
Target Markets
- Aerospace & Defense
- Automotive
- Broadcast
- Consumer
- High Performance Computing
- Industrial Scientific Medical
- Wired Communications
- Wireless Communications
Products and/or services provided by Alliance Program Members are sold or licensed solely by the Member and not Xilinx. Please be advised that Xilinx hereby disclaims any warranties, express or implied, including warranties of merchantability, fitness for a particular purpose, or noninfringement with respect to any such products and/or services.