NAND Flash Controller
- Part Number: iW-NAND Flash Controller
- Vendor: iWave Systems Technologies Pvt. Ltd.
- Partner Tier: Premier
Product Description
NAND Host Controller provides an easy interface to access NAND Flash Memory devices. This IP forms a bridge between the NAND flash and User (Processor), enabling to store, read and erase the data in NAND flash. The Controller has two different variants depending on the availability of the processor on the user side. One being the AXI-compliant interface for accessing through a processor and the other is a custom interface that can be used without the processor.
Key Features and Benefits
- Core is compliant with ONFI specification
- Supports both processor and non-processor environments with two different variants
- Controller supports rich set of NAND commands
- This IP will issue the necessary command address and controls all the necessary actions required to program, erase and read data using NAND flash
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-7000 Family | XC7Z020 | -1 | Vivado ML 2022.1 | Y | 505 | 836 | 1 | 0 | 0 | 0 | 143 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | R1.0 |
| Date Current Revision was Released | Jan 27, 2011 |
| Release Date of First Version | Jan 27, 2011 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 2 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq-7000 |
| Software Drivers Provided? | N |
| Driver OS Support | N/A |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | N |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | custom |
| Industry Standard Compliance Testing Passed | N |
| Specific Compliance Test | N/A |
| Are Test Results Available? | Y |