XpressRICH PCI Express 3.0/2.0/1.1 all-in-one (PLDA)
Part Number:
XpressRICH3
Alliance Program Tier:
Member
Design Tools Support:
- Vivado Design Suite
Device Family Support
- Kintex-7
- Virtex-7
PLDA PCIe 3.0/2.0/1.1 all-in-one Soft IP is a feature-rich, highly-configurable PCI Express endpoint and root port controller IP targeted to Xilinx FPGAs.The XpressRICH PCIe all-in-one IP is compliant to the PCI Express Base Specification Rev. 3.0 at Gen3, Gen2 and Gen1 speeds, as well as backward compatible to PCI Express Base Specification Rev. 2.0 and 1.1.
Key Features
- Backward compatible to PCI Express Base Specification Rev. 2.0 and 1.1
- Compliant to the PCI Express Base Specification Rev. 3.0 at Gen3, Gen2 and Gen1 speeds
Target Markets
- Aerospace & Defense
- Broadcast
- High Performance Computing
- Industrial Scientific Medical
- Wired Communications
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-7X Family | XC7VX485T | -2 | Vivado 2012.1 | Y | 0 | 28700 | 8 | 0 | 0 | 0 | 250 |
| KINTEX-7 Family | XC7K325T | -2 | Vivado 2012.1 | Y | 0 | 28700 | 8 | 0 | 0 | 0 | 250 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | May 23,2012 |
| Company Name | plda |
| IP Name | XpressRICH PCI Express 3.0/2.0/1.1 all-in-one (PLDA) |
| IP Part Number | XpressRICH3 |
| Current IP Revision Number | 1.0 |
| Date Current Revision was Released | Apr 01,2012 |
| Release Date of first Version | Feb 29,2012 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 10 |
| Can references be made available? | Y |
| Deliverables | |
| IP Formats available for purchase | Source Code |
| Source Code Formats(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Techbench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | N |
| FPGA used on board | N/A |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux 32/64-bit, Windows 32/64-bit |
| Implementation | |
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported / version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
| Verfification | |
| Is a documented verification plan available? | Yes, document only plan |
| Test Methodology | Both |
| Assertions | Y |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators supported | Mentor Questa |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | KC705, VC707 |
| Industry standard compliance testing passed | N |
| Are test results available? | N |
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