Create Timing Constraints™

Device Family Support

• Kintex-7
• Spartan-3
• Spartan-6 LX
• Virtex-4 LX
• Virtex-5 LX
• Virtex-6 LXT
• Virtex-7
• Zynq

Designs are increasingly becoming larger and more complex. They often have embedded processors, intellectual property, other pre-existing modules and multiple clocks. As these designs push the limits of area, power, and performance, the fastest timing routes quickly become congested and it gets more difficult to optimize for performance. Timing constraints, which include clock rates, I/O delays, and timing exceptions, direct the synthesis and place & route tools to achieve the necessary timing targets to meet performance requirements and close timing quickly.

Key Features

• Compares constraints in different SDC files
• Fast FSM and control behavior analysis
• Sequential analysis of false and multi-cycle paths

Target Markets

• Broadcast
• Automotive
• High Performance Computing
• Consumer
• Aerospace & Defense
• Industrial Scientific Medical
• Industrial Scientific Medical
• Wired Communications
• Wireless Communications