PCI Express 3.1 Controller
- Part Number: PCIe 3.1 XpressRICH
- Vendor: Rambus, Inc.
- Partner Tier: Elite
Product Description
The Rambus PCI Express® (PCIe) 3.1 Controller is designed to achieve maximum PCIe 3.1 performance with great design flexibility and ease of integration. It is fully compatible with the PCIe 3.1/3.0 specification. The controller delivers high-bandwidth and lowlatency connectivity for demanding applications in data center, edge and graphics.
Key Features and Benefits
- Supports Root Port, Endpoint, Switch Port, and Dual-Mode topologies
- Advanced features enable fine tuning of power, area, throughput and latency
- Internal data path size automatically scales up or down based on link max. speed and width
- Optional QuickBoot mode allows for up to 4x faster link training
- Supports advanced RAS features
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-UP Family | XCVU3P | -2 | Vivado ML 2022.2 | Y | 0 | 101826 | 8 | 0 | 0 | 0 | 250 |
| KINTEX-7 Family | XC7K325T | -2 | Vivado 2017.4 | Y | 0 | 28700 | 8 | 0 | 0 | 0 | 250 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 1.0 |
| Date Current Revision was Released | Apr 02, 2012 |
| Release Date of First Version | Mar 01, 2012 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 10 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | N |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux 32/64-bit, Windows 32/64-bit |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST; Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Both |
| Assertions | Y |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Mentor Questa |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | KC705, VC707 |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | PCI SIG Compliance test |
| Test Date | Aug 16, 2013 |
| Are Test Results Available? | Y |