HSR-PRP Switch IP Core
Part Number:
HSR-PRP Switch IP Core
AXI Interface Support:
- AXI4
License:
SignOnce
Alliance Program Tier:
Member
Design Tools Support:
- Vivado Design Suite
- ISE Design Suite
- IDS Embedded Edition
Device Family Support
- Spartan-6 LX
- Zynq-7000
HSR-PRPSwitch is an IP Core for the implementation of High-availability Seamless Redundancy and Parallel Redundancy Protocol (HSR and PRP, IEC 62439-3-Clause 5 and 4 respectively) protocols for Reliable Ethernet communications. HSR-PRPSwitch is a full hardware solution that can be implemented on a low-cost FPGA. It is a flexible solution for the Energy Market Equipments that will be connected to HSR rings, PRP Lans or will work as Network bridges.
Key Features
- 3us switching time for HSR modes
- All-in-hardware solution
- HSR and PRP in the same IP
- IEEE 1588 support
- Implementable on low-cost FPGAs
- No external RAM memory required
- SP605 and ZC702 Reference Designs
Target Markets
- Aerospace & Defense
- Automotive
- Industrial Scientific Medical
- Wired Communications
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool | Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | Fmax (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Spartan 6 Family | XC6SLX45 | -2 | ISE 13.2 | Y | 3474 | 9852 | 65 | 0 | 0 | 0 | 100 |
IP Quality Metrics Table
| General Information | |
| This Data was Current On | Mar 18,2013 |
| Company Name | Soc-e |
| IP Name | HSR-PRP Switch IP Core |
| IP Part Number | HSR-PRP Switch IP Core |
| Current IP Revision Number | 121024 |
| Date Current Revision was Released | Oct 11,2012 |
| Release Date of first Version | Jul 31,2012 |
| Production Use by Xilinx Customers | |
| Number of successful Xilinx Customer production projects | 1 |
| Can references be made available? | Y |
| Deliverables | |
| IP Formats available for purchase | Netlist |
| High-Level Model Included? | N |
| High-level Model Format(s) | Matlab |
| Integration Testbench Provided | Y |
| Integration Techbench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | Y |
| Commercial Evaluation Board Available? | Y |
| FPGA used on board | Spartan-6 |
| Software Drivers Provided? | Y |
| Driver OS Support | ANSI C |
| Implementation | |
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference; Instantiation |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported / version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| Standard IP Interface(s) Supported | AXI-4 |
| IP-XACT Metadata Included? | N |
| Verfification | |
| Is a documented verification plan available? | Executable and documented plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators supported | Xilinx lSim; Mentor ModelSIM |
| Hardware Validation | |
| Validated on FPGA | Y |
| Hardware validation platform used | sp605 |
| Industry standard compliance testing passed | Y |
| Specific compliance test | ZHAW Interoperability test |
| Test date | 2012-06-21 17:00:00.0 |
| Are test results available? | N |
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