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PCI Express Expresso DMA Core (NWL)

  • Part Number: Expresso DMA Core
  • Vendor: Northwest Logic
  • Ecosystem Program Tier: Certified

Product Description

The Northwest Logic Expresso DMA Core provides high-performance, scatter-gather DMA operation in a flexible fashion. This enables the core to be easily integrated and used in a wide variety of DMA-based systems. Using the core eliminates the need for users to implement their own DMA design, significantly reducing development time and risk.

Key Features and Benefits

  • Can be configured for up to 1024 DMA Channels
  • Companion Windows and Linux Expresso DMA Drivers available
  • Fully hardware validated
  • Provided with a PCI Express Testbench
  • Provides high performance, scatter-gather DMA operation
  • Supports AXI Master and Slave interfaces of selectable data widths 32, 64 , 128 or 256-bit
  • Supports Endpoint and Rootport applications
  • Supports PCIe Multi-Function and SRIOV capability
  • Supports legacy, MSI, MSI-X and local AXI interrupts
  • Utilization numbers provided in the IP Implementation and Quality Metrics are for a x1 lane PCIe implementation
  • Works with Xilinx PCI Express hard cores and Northwest Logic soft PCI Express cores

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -2 Vivado 2012.2 Y 11000 24200 3 0 0 0 250

IP Quality Metrics

General Information

This Data was Current On Oct 10, 2017
Current IP Revision Number 1.18
Date Current Revision was Released Feb 15, 2013
Release Date of First Version Apr 06, 2012

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 31
Can References be Made Available? Y


IP Formats Available for Purchase Netlist
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? UCF
Commercial Evaluation Board Available? N
Software Drivers Provided? Y
Driver OS Support Windows, Linux


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference
Custom FPGA Optimization Techniques Optimized levels of logic
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces , AXI4
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used multiple platforms
Industry Standard Compliance Testing Passed N/A
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