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MIPI DSI Controller Core (NWL)

  • Part Number: DSI Controller Core
  • License: SignOnce
  • Vendor: Northwest Logic
  • Ecosystem Program Tier: Certified

Product Description

The DSI Controller Core is part of Northwest Logic’s MIPI Solution. This solution is designed to achieve maximum MIPI throughput while being easy to use. The core implements all three layers defined by the DSI Specification: Pixel to Byte Packing, Low Level Protocol, and Lane Management and is fully compliant with the DSI specification. Separate Host (Tx) and Peripheral (Rx) versions of the core are provided. The core provides 4 data and 1 control/status packet interfaces. The data interfaces can be optional adapter to DBI or DPI interfaces. The control/status interface can be optionally adapted to an AXI interface. The core supports command and video modes, 1 to 4 data lanes and all data types. The core uses the byte lane clock minimizing power consumption and ensuring the core can be used in older process technologies. The core is delivered fully integrated and verified with the user’s target MIPI PHY. Contact Northwest Logic for a complete list of supported PHYs. The core is also provided with the MIPI Testbench which provides a MIPI Bus Functional Model. Northwest Logic also offers a DSI Demonstration System which includes an FPGA Board, MIPI Interface Card and MIPI Display. Contact Northwest Logic for more information.

Key Features and Benefits

  • Source code available
  • Provided with a MIPI DSI Testbench
  • Delivered fully integrated and verified with target MIPI PHY
  • 1-4 data lane support
  • Supports high speed (1+ Gbit/s) and low power operation
  • Support for all data types
  • Optional DBI & DPI data interface and AXI control/status interface adapters
  • 4 data and 1 control/status packet interfaces
  • Host (Tx) and Peripheral (Rx) versions
  • Fully DSI Specification compliant
  • High-performance, easy-to-use core

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-7 Family XC7K410T -2 Vivado 2018.2 Y 1250 2500 0 0 0 0 100

IP Quality Metrics

General Information

This Data was Current On Jan 11, 2019
Current IP Revision Number 1.24
Date Current Revision was Released Feb 02, 2017
Release Date of First Version Jan 28, 2011

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 9
Can References be Made Available? Y


IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex-7
Software Drivers Provided? N


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference
Custom FPGA Optimization Techniques Optimized levels of logic
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used multiple platforms
Industry Standard Compliance Testing Passed N/A
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