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PCIe Streaming DMA Controller

  • Part Number: DMA
  • Vendor: Omnitek
  • Program Tier: Premier

Product Description

Multi-channel Streaming DMA Controller for PCI Express offering both memory-based ‘MDMA’ for handling transfers to and from addressed memory such as on-board SRAM and SDRAM, and FIFO-based ‘FDMA’ for streaming applications. Offered in 1, 2, 4 and 8 Lane versions. Multi-channel option, interface width selection (64, 128 or 256) and PCIe Generation 1, 2 & 3 support. Peer-to-peer custom option. Supplied in encrypted source format. Windows + Linux Driver source example for OEM ID insertion.


Key Features and Benefits

  • Drivers & API
  • Encrypted RTL
  • Free Evaluation
  • Project Integration File
  • Reference Design
  • Support & Maintenance
  • Testbench

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -1 Vivado 2014.2 Y 5048 10298 50 0 0 8 250000000

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 1.06.a
Date Current Revision was Released Oct 15, 2014
Release Date of First Version Jul 11, 2013

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 40
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code
Source Code Format(s) VHDL, Verilog
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex-7
Software Drivers Provided? Y
Driver OS Support Windows & Linux

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation, UltraFast Design Methodology, Inference
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST / 14.7
Static Timing Analysis Performed? N
AXI Interfaces AXI4, AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM / 10.1

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KC705
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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